Semiconductor device packages with electromagnetic interference shielding

• US 8,212,339 B2
• Filed: 04/29/2010
• Issued: 07/03/2012
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liao, Kuo-Hsien, Chen, Jian-Cheng, Fan, Chen-Chuan, Chiu, Chi-Tsung, Hung, Chih-Pin
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US12/770,645
• Publication Number:
  US 20100207259A1
• Time in Patent Office: 796 Days
• Field of Search: 257/659, 257/660, 257/E23.114, 257/E23.115, 257/E21.499, 438/121
• US Class Current: 257/659
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Claims

1. A semiconductor device package, comprising:

a substrate unit including an upper surface, a lower surface, a lateral surface disposed adjacent to a periphery of the substrate unit and fully extending between the upper surface and the lower surface of the substrate unit, and a grounding element disposed adjacent to the periphery of the substrate unit and at least partially extending between the upper surface and the lower surface of the substrate unit, the grounding element including an indented portion that is disposed adjacent to the lateral surface of the substrate unit;

a semiconductor device electrically connected to the substrate unit;

a package body disposed adjacent to the upper surface of the substrate unit and encapsulating the semiconductor device, the package body including exterior surfaces that include a lateral surface; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and the lateral surface of the substrate unit, the electromagnetic interference shield being electrically connected to the grounding element;

wherein the grounding element includes a connection surface that is inwardly recessed relative to the lateral surface of the substrate unit, and the electromagnetic interference shield conformally coats the connection surface.

2. The semiconductor device package of claim 1, wherein the grounding element includes a plated channel remnant that corresponds to the indented portion of the grounding element, and a filler material located within the indented portion.

3. The semiconductor device package of claim 1, wherein the grounding element partially extends between the upper surface and the lower surface of the substrate unit, such that a height of the grounding element is less than a thickness of the substrate unit.

4. The semiconductor device package of claim 1, wherein the lateral surface of the substrate unit is substantially planar, and the lateral surface of the package body is substantially aligned with the lateral surface of the substrate unit.

5. The semiconductor device package of claim 1, wherein the grounding element further includes a non-conductive filler material located within the indented portion.

6. A semiconductor device package, comprising:

a substrate unit including an upper surface, a lower surface, a lateral surface disposed adjacent to a periphery of the substrate unit and fully extending between the upper surface and the lower surface of the substrate unit, and a grounding element disposed adjacent to the periphery of the substrate unit and at least partially extending between the upper surface and the lower surface of the substrate unit, the grounding element including an indented portion that is disposed adjacent to the lateral surface of the substrate unit;

a semiconductor device electrically connected to the substrate unit;

a package body disposed adjacent to the upper surface of the substrate unit and encapsulating the semiconductor device, the package body including exterior surfaces that include a lateral surface; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and the lateral surface of the substrate unit, the electromagnetic interference shield being electrically connected to the grounding element;

wherein the grounding element partially extends between the upper surface and the lower surface of the substrate unit, such that a height of the grounding element is less than a thickness of the substrate unit; and

wherein the substrate unit includes a pair of internal grounding layers, and the grounding element extends between the pair of internal grounding layers.

7. The semiconductor device package of claim 6, wherein the grounding element includes a connection surface that is inwardly recessed relative to the lateral surface of the substrate unit, and the electromagnetic interference shield conformally coats the connection surface.

8. A semiconductor device package, comprising:

a substrate including a first surface, a second opposing surface, and a grounding element at least partially extending between the first surface and the second opposing surface of the substrate, the grounding element including a plated channel remnant and a filler member, the plated channel remnant being inwardly recessed so as to accommodate the filler member, the plated channel remnant and the filler member defining a lateral surface of the grounding element that is disposed adjacent to a periphery of the substrate;

a semiconductor device electrically connected to the substrate;

a package body disposed adjacent to the first surface of the substrate and encapsulating the semiconductor device, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the lateral surface of the grounding element, wherein a lateral profile of the semiconductor device package is substantially planar and is substantially orthogonal with respect to the second opposing surface of the substrate;

wherein the lateral surface of the grounding element is substantially planar.

9. The semiconductor device package of claim 8, wherein the grounding element partially extends between the first surface and the second opposing surface of the substrate, such that a height of the grounding element is less than a thickness of the substrate.

10. The semiconductor device package of claim 8, wherein the filler member is electrically non-conductive.

11. The semiconductor device package of claim 8, wherein the substrate further includes a lateral surface fully extending between the first surface and the second opposing surface of the substrate, the lateral surface of the substrate is substantially planar and is substantially orthogonal with respect to the second opposing surface of the substrate, and the lateral surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate.

12. The semiconductor device package of claim 8, wherein the exterior surfaces of the package body include a lateral surface, and the lateral surface of the package body is substantially aligned with a lateral surface of the substrate.

13. The semiconductor device package of claim 8, wherein the grounding element further includes a first via pad remnant and a second via pad remnant, and the plated channel remnant extends between the first via pad remnant and the second via pad remnant.

14. The semiconductor device package of claim 13, wherein the substrate further includes an electrically conductive layer disposed between the first surface and the second opposing surface of the substrate, the first via pad remnant is disposed adjacent to the electrically conductive layer of the substrate, and the second via pad remnant is disposed adjacent to the second opposing surface of the substrate.

15. The semiconductor device package of claim 8, wherein the electromagnetic interference shield is a conformal shield that includes a first layer and a second layer disposed adjacent to the first layer.

16. The semiconductor device package of claim 15, wherein the first layer and the second layer include different electrically conductive materials.

17. A semiconductor package, comprising:

a substrate including a lateral surface and a grounding element including a partial annular portion recessed from the lateral surface of the substrate and a filler material disposed in a recess defined by the partial annular portion, wherein the partial annular portion has at least one sidewall exposed;

a package body disposed adjacent to an upper surface of the substrate, the package body including exterior surfaces that include a lateral surface; and

a shielding layer disposed adjacent to the exterior surfaces of the package body and the lateral surface of the substrate, wherein the shielding layer is physically connected to the at least one sidewall of the partial annular portion;

wherein the partial annular portion and the filler material define a lateral surface of the grounding element that is disposed adjacent to the lateral surface of the substrate, and that is substantially planar.

18. The semiconductor package of claim 17, wherein the grounding element partially extends between the upper surface and a lower surface of the substrate, such that a height of the grounding element is less than a thickness of the substrate.

19. The semiconductor package of claim 17, wherein the filler material is electrically non-conductive.

20. The semiconductor package of claim 17, wherein the lateral surface of the substrate fully extends between a first surface and a second opposing surface of the substrate, and the lateral surface of the substrate is substantially planar.