Chip package and manufacturing method thereof

• US 8,212,340 B2
• Filed: 07/13/2009
• Issued: 07/03/2012
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liao, Kuo-Hsien
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US12/501,636
• Publication Number:
  US 20110006408A1
• Time in Patent Office: 1,086 Days
• Field of Search: 257/660, 257/E23.114
• US Class Current: 257/660
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A chip package including a shielding layer conformally covering the underlying molding compound for is provided. The shielding layer can smoothly cover the molding compound and over the rounded or blunted, top edges of the molding compound, which provides better electromagnetic interferences shielding and better shielding performance.

Claims

1. A semiconductor package, comprising:

a substrate;

a molding compound disposed adjacent to the substrate and including an upper surface, a sidewall, and a connecting section that extends from the upper surface to the sidewall, the connecting section including a first planar surface and a second planar surface that incline away from the upper surface; and

a shielding layer disposed adjacent to the molding compound, wherein the shielding layer conformally covers the upper surface, the sidewall, and the connecting section of the molding compound, and the shielding layer is electrically connected to the substrate,

wherein the first planar surface and the second planar surface define an obtuse angle in the range from 100 degrees to 160 degrees that faces inwardly toward the molding compound.

2. The semiconductor package as claimed in claim 1, wherein the second planar surface and the sidewall define an obtuse angle.

3. The semiconductor package as claimed in claim 1, wherein the upper surface and the first planar surface define an obtuse angle in the range from 95 degrees to 165 degrees.

4. The semiconductor package as claimed in claim 1, wherein the first planar surface and the second planar surface define a contiguous arc.

5. The semiconductor package as claimed in claim 1, wherein:

the shielding layer at least partially covers a lateral surface of the substrate.

14. The semiconductor package as claimed in claim 1, wherein the shield at least partially covers a lateral surface of the substrate, and the lateral surface of the substrate is substantially co-planar with the lateral surface of the package body.

6. A semiconductor package, comprising:

a substrate;

a molding compound disposed adjacent to the substrate and including an upper surface, a sidewall, and a connecting section that extends from the upper surface to the sidewall, the connecting section including a first surface that inclines away from the upper surface; and

a shielding layer disposed adjacent to the molding compound, wherein the shielding layer conformally covers the upper surface, the sidewall, and the connecting section of the molding compound, and the shielding layer is electrically connected to the substrate,

wherein

the first surface is planar;

the connecting section includes a second surface that is planar and that extends from the first surface; and

the second surface is not orthogonal to the first surface,

wherein the first surface and the second surface define an obtuse angle in the range from 100 degrees to 160 degrees that faces inwardly toward the molding compound.

7. The semiconductor package as claimed in claim 6, wherein:

the first surface is a first beveled surface, and the second surface is a second beveled surface that is contiguous with the first beveled surface.

8. The semiconductor package as claimed in claim 6, wherein the substrate includes a ground via, wherein the shielding layer physically contacts a side surface of the ground via.

9. The semiconductor package as claimed in claim 8, wherein the shielding layer fully covers the side surface of the ground via.

10. A semiconductor package, comprising:

a substrate;

a package body including a lateral surface, an upper surface, and an edge portion circumscribing the upper surface, wherein the lateral surface is substantially perpendicular to the upper surface, and wherein the first edge portion includes a first beveled surface and a second beveled surface, each of which slopes downwardly and outwardly from the upper surface toward the lateral surface, and wherein the first beveled surface and the second beveled surface define an obtuse angle in the range from 100 degrees to 160 degrees that faces inwardly toward the package body; and

a shield covering the package body, wherein the shield physically contacts at least the upper surface and the edge portion.

11. The semiconductor package as claimed in claim 10, wherein:

the second beveled surface and the lateral surface define an obtuse angle.

12. The semiconductor package as claimed in claim 10, wherein:

the upper surface and the first beveled surface define an obtuse angle in the range from 95 degrees to 165 degrees.

13. The semiconductor package as claimed in claim 10, wherein the first beveled surface is contiguous with the second beveled surface.

15. A semiconductor package, comprising:

a substrate;

a chip disposed on and electrically connected to the substrate; and

a shield disposed over the chip, wherein the shield includes an upper surface, a lateral periphery circumscribing the upper surface, and a connecting section extending from the upper surface to the lateral periphery, wherein;

the connecting section includes a first portion extending from the upper surface, wherein the first portion and the upper surface define a first obtuse angle, and a second portion extending from the first portion to the lateral periphery, wherein the first portion and the second portion define a second obtuse angle that faces inwardly toward the chip.

16. The semiconductor package as claimed in claim 15, wherein the connecting section defines a contiguous arc.

17. The semiconductor package as claimed in claim 15, wherein the first obtuse angle faces inwardly toward the chip.

18. The semiconductor package as claimed in claim 15, wherein the second portion is substantially planar.

19. The semiconductor package as claimed in claim 15, wherein a junction of the first portion and the second portion defines an apex.

20. The semiconductor package as claimed in claim 15, wherein the second obtuse angle is less than the first obtuse angle.