Shared bit line and source line resistive sense memory structure
First Claim
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1. A spin transfer torque memory apparatus comprising:
- a first transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first spin transfer torque memory element;
a second transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second spin transfer torque memory element; and
a bit line electrically connected to the first spin transfer torque memory element and the second spin transfer torque memory element at the same location on the bit line.
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Abstract
A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.
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Citations
20 Claims
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1. A spin transfer torque memory apparatus comprising:
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a first transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first spin transfer torque memory element; a second transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second spin transfer torque memory element; and a bit line electrically connected to the first spin transfer torque memory element and the second spin transfer torque memory element at the same location on the bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A spin transfer torque memory apparatus comprising:
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a first transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first spin transfer torque memory element; a second transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second spin transfer torque memory element; a bit line electrically connected to the first spin transfer torque memory element and the second spin transfer torque memory element at the same location on the bit line; and a third transistor sharing the first contact electrically connected to the first source line at the first contact location, the third transistor having a second contact electrically connected to a third spin transfer torque memory element, and the third resistive spin transfer torque element electrically connected to a second bit line. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of accessing a spin transfer torque memory cell in a memory array comprising:
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providing a spin transfer torque memory array comprising; a first transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first spin transfer torque memory element; a second transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second spin transfer torque memory element; a bit line electrically connected to the first spin transfer torque memory element and the second spin transfer torque memory element at the same location on the bit line; and a third transistor sharing the first contact electrically connected to the first source line at the first contact location, the third transistor having a second contact electrically connected to a third spin transfer torque memory element, and the third spin transfer torque memory element electrically connected to a second bit line; applying a source voltage to the first source line and the second bit line; applying a drain voltage to the first bit line and second source line; and applying a gate voltage to the first transistor, second transistor and third transistor to flow current through the first spin transfer torque memory element. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification