Non-volatile semiconductor memory with page erase

• US 8,213,240 B2
• Filed: 06/27/2011
• Issued: 07/03/2012
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Lam, David
• Application Number:
  US13/169,231
• Publication Number:
  US 20110267896A1
• Time in Patent Office: 372 Days
• Field of Search: 365/185.29, 365/185.17, 365/185.18, 365/185.12, 365/185.27, 365/185.23
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Claims

1. A method for performing a page erase operation in a nonvolatile memory array having

plural strings of memory cells on a substrate, and

plural wordlines across the strings to pages of memory cells;

and

associated with plural pass transistors, each of which is configured to apply a voltage to a respective one of the wordlines,

the memory array being divided into plural blocks, the method comprising;

selecting at least one of the blocks;

selecting any one or ones of the wordlines of the selected block;

enabling each of the pass transistors associated with the selected block;

applying a select voltage to the selected one or ones of the wordlines of the selected block;

applying an unselect voltage to unselected one or ones of the wordlines that are other than the selected one or ones of the wordlines of the selected block; and

applying a substrate voltage to the substrate of the selected block,

the voltage difference between the substrate voltage and the select voltage causing the page or pages of memory cells coupled to the selected one or ones of the wordlines to be erased, and

the voltage difference between the substrate voltage and the unselect voltage not causing the page or pages of memory cells coupled to the unselected one or ones of the wordlines of the selected block to be erased.

2. The method of claim 1 wherein:

the applying a select voltage comprises applying the select voltage to one or ones of the pass transistors coupled to the selected one or ones of the wordlines of the selected block; and

the applying an unselect voltage comprises applying the unselect voltage to one or ones of the pass transistors coupled to the unselected one or ones of the wordlines of the selected block.

3. The method of claim 1 wherein the selected wordlines are separated by at least one of the unselected wordlines.

4. The method of claim 1 wherein the unselected wordlines are separated by at least one of the selected wordlines.

5. The method of claim 1 wherein a resulting voltage of the selected wordlines is substantially the same as the select voltage and a resulting voltage of the unselected wordlines is substantially the same as the unselect voltage.

6. The method of claim 1 wherein the select voltage is about zero volts and the unselect voltage is about equal to the applied substrate voltage.

7. The method of claim 1 wherein a resulting voltage of the selected wordlines is substantially the same as the select voltage and a resulting voltage of the unselected wordlines is a floating voltage coupled from the unselect voltage toward the substrate voltage.

8. The method of claim 1 wherein the applying an unselect voltage comprises applying a boosted voltage.

9. A nonvolatile memory comprising:

a memory array comprising plural strings of memory cells on a substrate and plural wordlines across the strings to pages of memory cells, the memory array being divided into plural blocks;

plural pass transistors, each of which is configured to apply a voltage to a respective one of the wordlines;

a block selector for selecting at least one of the blocks to enable each of the pass transistors in the selected block during an erase operation;

a substrate voltage source for applying a substrate voltage to the substrate during the erase operation; and

a wordline decoder for selecting any one or ones of the wordlines of the selected block to apply

a select voltage to the selected one or ones of the wordlines to erase one or ones of the pages of memory cells coupled to the selected one or ones of the wordlines of the selected block and

an unselect voltage to unselected one or ones of the wordlines that are other than the selected one or ones of the wordlines of the selected block,

the wordline decoder being configured to respond to address instructions to apply the select voltage to the selected one or ones of the wordlines of the selected block and to apply the unselect voltage to the unselected one or ones of the wordlines of the selected block.

10. The memory of claim 9 wherein the wordline decoder is adapted to apply the select voltage to any of the wordlines and the unselect voltage to any of the wordlines.

11. The memory of claim 9 wherein a resulting voltage of the selected wordlines is substantially the same as the select voltage and a resulting voltage of the unselected wordlines is substantially the same as the unselect voltage.

12. The memory of claim 9 wherein the select voltage is about zero volts and the unselect voltage is about equal to the applied substrate voltage.

13. The memory of claim 9 wherein a resulting voltage of the selected wordlines is substantially the same as the select voltage and a resulting voltage of the unselected wordlines is a floating voltage coupled from the unselect voltage toward the erase voltage.

14. The memory of claim 9 wherein a gate signal to each of the pass transistors has a value V₂, the unselect voltage is greater than V₂and the unselected one or ones of the wordlines precharge to V₂−

V_tn, and wherein V₂ is substantially less than the applied substrate voltage.

15. The memory of claim 14 wherein V₂ is at least 50% of the erase voltage.

16. The memory of claim 9 wherein the pass transistors coupled to the wordlines of unselected one or ones of the blocks that are other than the selected at least one of the blocks are gated off after a voltage less than the unselect voltage is applied to each of the pass transistors and the wordlines float to prevent erasure.

17. The memory of claim 9 wherein the unselect voltage is closer to the erase voltage applied to the substrate than to the select voltage.

18. The memory of claim 9 wherein the wordline decoder is configured to apply a boosted voltage as the unselect voltage.