Semiconductor memory device having improved local input/output line precharge scheme
First Claim
1. A data path circuit of a semiconductor memory device, the data path circuit comprising:
- a bit line sense amplifier adapted to be driven by a first power supply voltage;
a local input/output line sense amplifier;
a column selecting unit adapted to operatively connect a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and
a local input/output line precharge unit adapted to precharge the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state.
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Accused Products
Abstract
A data path circuit of a semiconductor memory device includes: a bit line sense amplifier driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit operatively connecting a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and a local input/output line precharge unit precharging the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state.
382 Citations
14 Claims
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1. A data path circuit of a semiconductor memory device, the data path circuit comprising:
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a bit line sense amplifier adapted to be driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit adapted to operatively connect a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and a local input/output line precharge unit adapted to precharge the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor memory device, comprising:
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a memory cell array including a plurality of memory cells, each having one access transistor and one storage capacitor, arranged in a matrix; a bit line sense amplifier connected to a pair of bit lines connected to the memory cells and adapted to be driven by a first power supply voltage; a local input/output line sense amplifier connected between a pair of global input/output lines and a pair of local input/output lines; a column selecting unit adapted to operatively connect the pair of bit lines and the pair of local input/output lines in response to a column selection signal; and a local input/output line precharge unit adapted to precharge the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A dynamic random access memory, comprising:
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a memory cell array including a plurality of memory cells, each including one access transistor and one storage capacitor, arranged in a matrix; a bit line sense amplifier connected to a pair of bit lines connected to the memory cells and adapted to be driven by a first power supply voltage; a local input/output line sense amplifier connected between a pair of global input/output lines and a pair of local input/output lines and having a bias current that is adjusted by a second power supply voltage lower than the first power supply voltage; a column selecting unit adapted to operatively connect the pair of bit lines and the pair of local input/output lines in response to a column selection signal; a local input/output line precharge unit adapted to precharge the pair of local input/output lines with the second power supply voltage during a period for which the column selection signal is in an inactive state; a signal generating unit adapted to receive signals related to read/write commands and to generate a period pulse signal for setting a detection operation period; a level detecting unit adapted to be enabled in response to the period pulse signal, to compare a reference signal with the second power supply voltage that is fed back, and to output a driving enable signal; and a voltage driver adapted to generate the second power supply voltage in response to the driving enable signal and to apply the second power supply voltage to the local input/output line precharge unit and the local input/output line sense amplifier. - View Dependent Claims (14)
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Specification