Variation-tolerant word-line under-drive scheme for random access memory

• US 8,213,257 B2
• Filed: 08/09/2010
• Issued: 07/03/2012
• Est. Priority Date: 08/09/2010
• Status: Active Grant

• Current Assignee: Faraday Technology Corp., National Chiao Tung University (Government of The Republic of China)
• Original Assignee: Faraday Technology Corp., National Chiao Tung University (Government of The Republic of China)
• Inventors: Chuang, Ching-Te, Lin, Yi-Wei, Chen, Chia-Cheng, Shih, Wei-Chiang
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US12/852,759
• Publication Number:
  US 20120033522A1
• Time in Patent Office: 694 Days
• Field of Search: 365/230.06, 365/214, 365/189.05
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Claims

1. A Random Access Memory (RAM), comprising:

a plurality of rows, each of the rows comprising a plurality of cells and a corresponding word-line;

each cell comprising a latch for storing data, and at least a pass-gate transistor coupled between the latch, the corresponding word-line and a corresponding bit-line;

a plurality of word-line drivers, each of the word-line driver comprising a power node receiving an operation voltage, a driving node coupled to one of the word-lines of the rows, an input node receiving a decoding signal, and a driving transistor comprising a control node and two channel terminal nodes respectively coupled to the input node, the driving node, and the power node;

at least a first tracking transistor, corresponding to one of the word-line driver, comprising two channel terminal nodes with one of the two channel terminal nodes coupled to one of the driving node, and the other channel terminal node coupled to one of the two channel terminal nodes of a second tracking transistors;

the first tracking transistor having electronic characteristics tracking those of the pull-up driving transistor of the corresponding word-line driver; and

at least a second tracking transistor comprising two channel terminal nodes with one of the two channel terminal nodes coupled to one of the two channel terminal nodes of the first tracking transistor, the second tracking transistor having electronic characteristics tracking those of the pass-gate transistors of the cells.

2. The RAM of claim 1 comprising a plurality of the first tracking transistors and a plurality of the second tracking transistors, each of the first tracking transistors corresponding to one of the word-line drivers, each of the second tracking transistors corresponding to one of the first tracking transistors, the two channel terminal nodes of each of the first tracking transistors respectively coupled to the driving node of the corresponding word-line driver and one of the two channel terminal nodes of the corresponding second tracking transistor.

3. The RAM of claim 2, wherein the power node of each of the word line drivers is coupled to a first voltage source, each of the first tracking transistors further comprises a control node coupled to a second voltage source, and each of the second tracking transistors further comprises a control node coupled to the driving node of the corresponding word line driver.

4. The RAM of claim 2, wherein the power node of each of the word-line drivers is coupled to a first voltage source, each of the first tracking transistors further comprises a control node coupled to the input node of the corresponding word-line driver, and each of the second tracking transistors further comprises a control node coupled to the driving node of the corresponding word-line driver.

5. The RAM of claim 1 comprising a plurality of the first tracking transistors and one second tracking transistor, each of the first tracking transistors corresponding to one of the word-line driver, the second tracking transistor being a shared second tracking transistor, the two channel terminal nodes of each of the first tracking transistors respectively coupled to the driving node of the corresponding word-line driver and one of the two channel terminal nodes of the shared second tracking transistor.

6. The RAM of claim 1, wherein the two channel terminal nodes of the first tracking transistor are respectively coupled to a first voltage source and the power nodes of the word-line drivers, one of the two channel terminal nodes of the second tracking transistor is coupled to the power nodes of the world-line drivers.

7. The RAM of claim 1 comprising a plurality of the first tracking transistors and a plurality of the second tracking transistors;

each of the first tracking transistors further comprising a control node;

one of the first tracking transistors being a power-side first tracking transistor, the others of the first tracking transistors being driving-side first tracking transistors;

one of the second tracking transistors being a power-side second tracking transistor, the others of the second tracking transistors being driving-side second tracking transistors;

the control node and the two channel terminal nodes of the power-side first tracking transistor respectively coupled to a second voltage source, a first voltage source, and the power nodes of the word-line drivers;

each of the driving-side second tracking transistors respectively corresponding to one of the driving-side first tracking transistors;

the control node and the two channel terminal nodes of each of the driving-side first tracking transistors respectively coupled to the second voltage source, the driving node of one of the word-line drivers, and one of the two channel terminal nodes of the corresponding driving-side second tracking transistor.

8. The RAM of claim 1 comprising a plurality of the first tracking transistors and a plurality of the second tracking transistors;

each of the first tracking transistors further comprising a control node;

one of the first tracking transistors being a power-side first tracking transistor, the others of the first tracking transistors being driving-side first tracking transistors;

one of the second tracking transistors being a power-side second tracking transistor, the others of the second tracking transistors being driving-side second tracking transistors;

each of the driving-side first tracking transistors respectively corresponding to one of the driving-side second tracking transistors and one of the word-line drivers;

the control node and the two channel terminal nodes of power-side first tracking transistors respectively coupled to a second voltage source, a first voltage source, and the power nodes of the word-line drivers;

the control node and the two channel terminal nodes of each of the driving-side first tracking transistors respectively coupled to the input node. The driving node of the corresponding word-line driver, and one of the two channel terminal nodes of the corresponding driving-side second tracking transistor.

9. The RAM of claim 1 comprising a plurality of the first tracking transistors and a plurality of the second tracking transistors;

each of the first tracking transistors further comprising a control node;

one of the first tracking transistors being a power-side first tracking transistor, the others of the first tracking transistors being driving-side first tracking transistors;

one of the second tracking transistors being a power-side second tracking transistor with a different one of the second tracking transistors being a shared driving-side second tracking transistor;

each of the driving-side first tracking transistors respectively corresponding to one of the word-line drivers;

the control node and the two channel terminal nodes of the power-side first tracking transistors respectively coupled to a second voltage source, a first voltage source, and the power nodes of the word-line drivers;

the control node and the two channel terminal nodes of each of the driving-side first tracking transistors respectively coupled to the input node, the driving node of the corresponding word-line driver, and one of the two channel terminal nodes of the shared driving-side second tracking transistor.

10. The RAM of claim 1 comprising a plurality of the first tracking transistors and a plurality of the second tracking transistors;

each of the word-line drivers corresponding to one of the first tracking transistors and one of the second tracking transistors with one of the two channel terminal nodes of the corresponding first tracking transistor and one of the two channel terminal nodes of the corresponding second tracking transistor both coupled to the driving node.

11. The RAM of claim 1 comprising a plurality of the first tracking transistors and a plurality of the second tracking transistors, each of the word-line drivers corresponding to one of the first tracking transistors and two of the second tracking transistors respectively being a shunt second tracking transistor and a serial second tracking transistor, with the two channel terminal nodes of the first tracking transistor respectively coupled to the driving node and one of the two channel terminal nodes of the serial second tracking transistor, and the control node of the shunt second transistor coupled to the driving node.

12. The RAM of claim 1 comprising a plurality of the first tracking transistors and a plurality of the second tracking transistors;

the word-line drivers corresponding to a shared second tracking transistor of the second tracking transistors;

wherein each of the word-line drivers further corresponds to one of the first tracking transistors and one of the second tracking transistors, being a shunt second tracking transistor, besides the shared second tracking transistor, the channel terminal nodes of the corresponding first tracking transistor are respectively coupled to the driving node and one of the two channel terminal nodes of the shared second tracking transistor, and one of the two channel nodes of the corresponding shunt second transistor is coupled to the driving node.