Systems and methods providing ASICs for use in multiple applications
First Claim
Patent Images
1. A system comprising:
- an application specific integrated circuit (ASIC) comprising;
a plurality of components for providing a first level of signal channel reduction and a second level of signal channel reduction, wherein said first and second levels of signal channel reduction are achieved by selecting which of said components to enable; and
a plurality of multiplexers providing N to M signal multiplexing,wherein in the first level of signal channel reduction said ASIC is configured to provide N to M signal multiplexing;
wherein in the second level of signal channel reduction said ASIC is configured to provide N to M/2 signal multiplexing;
wherein said plurality of multiplexers include N signal inputs, M signal outputs, at least one select signal input, and at least one enable signal input, said enable signal input being utilized in providing said N to M/2 signal multiplexing in said second level of signal channel reduction; and
wherein said plurality of multiplexers are divided into hardwired pairs, and only one of each pair is enabled during a receive operation.
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Abstract
A system comprises an application specific integrated circuit (ASIC) adapted for use in a plurality of circuit configurations. The circuit configurations provide for different numbers of signal channels for further processing using same circuitry of said application specific integrated circuit.
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Citations
19 Claims
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1. A system comprising:
an application specific integrated circuit (ASIC) comprising; a plurality of components for providing a first level of signal channel reduction and a second level of signal channel reduction, wherein said first and second levels of signal channel reduction are achieved by selecting which of said components to enable; and a plurality of multiplexers providing N to M signal multiplexing, wherein in the first level of signal channel reduction said ASIC is configured to provide N to M signal multiplexing; wherein in the second level of signal channel reduction said ASIC is configured to provide N to M/2 signal multiplexing; wherein said plurality of multiplexers include N signal inputs, M signal outputs, at least one select signal input, and at least one enable signal input, said enable signal input being utilized in providing said N to M/2 signal multiplexing in said second level of signal channel reduction; and wherein said plurality of multiplexers are divided into hardwired pairs, and only one of each pair is enabled during a receive operation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:
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determining a number of signal channels for use in a data path; configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction; and summing data on each of at least two channels by the ASIC, wherein summing data comprises;
receiving signals from a control circuit instructing that certain of the channels are to be divided into symmetric pairs and those pairs added, thereby decreasing the number of output channels; and
routing the added pairs to one or more beam formers. - View Dependent Claims (8, 9, 10, 11)
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12. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:
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determining a number of signal channels for use in a data path; configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction; and summing data on each of at least two channels by the ASIC, wherein summing data comprises;
receiving signals from a control circuit instructing that certain of the channels are to be divided into adjacent pairs and those pairs added, thereby decreasing the number of output channels; and
routing the added pairs to one or more beam formers. - View Dependent Claims (13, 14, 15, 16)
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17. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:
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determining a number of signal channels for use in a data path; configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction; implementing two beam formers in communication with the data path; and operating the two beam formers and a transducer array to form multiple receive beams. - View Dependent Claims (18)
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19. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:
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determining a number of signal channels for use in a data path; configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction; implementing a signal processing unit to communicate with the data path at a number of points; programming the signal processing unit with code to provide a mode of functionality not originally included in a platform using the method; and operating the signal processing unit to intercept and insert data along the number of points on the path, thereby instructing the platform to perform the mode.
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Specification