Methods and apparatus for dynamic packet reordering
First Claim
1. A method for processing slot data on-the-fly to produce decodable packets, wherein the slot data comprises interleaved modulation symbols, the method comprising:
- de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols;
calculating parallel streams of LLR metrics based on the stream of modulation symbols;
generating control signals to map the parallel streams of LLR metrics into a packet buffer; and
producing a stream of decodable packets from the packet buffer based on the parallel streams of LLR metrics and the control signals.
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Accused Products
Abstract
Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.
47 Citations
58 Claims
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1. A method for processing slot data on-the-fly to produce decodable packets, wherein the slot data comprises interleaved modulation symbols, the method comprising:
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de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols; calculating parallel streams of LLR metrics based on the stream of modulation symbols; generating control signals to map the parallel streams of LLR metrics into a packet buffer; and producing a stream of decodable packets from the packet buffer based on the parallel streams of LLR metrics and the control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. Apparatus for processing slot data on-the-fly to produce decodable packets, wherein the slot data comprises interleaved modulation symbols, the apparatus comprising:
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de-interleaving hardware logic configured to de-interleave a stream of the interleaved modulation symbols to produce a stream of modulation symbols; metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols; mapping logic configured to generate control signals to map the parallel streams of LLR metrics into a packet buffer; and output logic configured to produce a stream of decodable packets from the packet buffer based on the parallel streams of LLR metrics and the control signals. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. Apparatus for processing slot data on-the-fly to produce decodable packets, wherein the slot data comprises interleaved modulation symbols, the apparatus comprising:
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means for de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols; means for calculating parallel streams of LLR metrics based on the stream of modulation symbols;
means for generating control signals to map the parallel streams of LLR metrics into a packet buffer; andmeans for producing a stream of decodable packets from the packet buffer based on the parallel streams of LLR metrics and the control signals. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A non-transitory computer-readable storage medium comprising a computer program, which when executed by at least one processor, operates to process slot data on-the-fly to produce decodable packets, wherein the slot data comprises interleaved modulation symbols, the computer program comprising:
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instructions for de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols; instructions for calculating parallel streams of LLR metrics based on the stream of modulation symbols; instructions for generating control signals to map the parallel streams of LLR metrics into a packet buffer; and instructions for producing a stream of decodable packets from the packet buffer based on the parallel streams of LLR metrics and the control signals. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. A processor configured to process slot data on-the-fly to produce decodable packets, wherein the slot data comprises interleaved modulation symbols, the processor comprising:
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a first hardware module for de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols; a second module for calculating parallel streams of LLR metrics based on the stream of modulation symbols; a third module for generating control signals to map the parallel streams of LLR metrics into a packet buffer; and a fourth module for producing a stream of decodable packets from the packet buffer based on the parallel streams of LLR metrics and the control signals. - View Dependent Claims (54, 55, 56, 57, 58)
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Specification