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Cross-architecture execution optimization

  • US 8,214,191 B2
  • Filed: 01/31/2006
  • Issued: 07/03/2012
  • Est. Priority Date: 08/29/2005
  • Status: Active Grant
First Claim
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1. A device comprising:

  • an input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture; and

    a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data.

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