Cross-architecture execution optimization

• US 8,214,191 B2
• Filed: 01/31/2006
• Issued: 07/03/2012
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Hillis, W. Daniel, Mangione-Smith, William Henry, Myhrvold, Nathan P., Tegreene, Clarence T., Wood, Lowell L. Jr.
• Primary Examiner(s): Thangavelu, Kandasamy
• Application Number:
  US11/343,927
• Publication Number:
  US 20070050609A1
• Time in Patent Office: 2,345 Days
• Field of Search: 703/26, 703/22, 703/20, 717/136, 717/155, 717/158, 717/144, 717/119, 717/149, 717/137, 717/161, 717/141, 717/146, 717/135, 712/36, 712/237, 716/5
• US Class Current: 703/22
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring

Abstract

Embodiments include a device, apparatus, and a method. A device includes an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture. The device also includes a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture.

Claims

1. A device comprising:

an input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture; and

a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data.

2. The device of claim 1, wherein the input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture includes

an input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first instruction set architecture.

3. The device of claim 1, wherein the input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture includes

an input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first microarchitecture.

4. The device of claim 1, wherein the input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture includes

an input circuit configured for receiving data corresponding to a runtime execution of a first instruction associated with a program that is executed by a first processor having a first architecture.

5. The device of claim 4, wherein the generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data includes

a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction associated with the program by a second processor having a second architecture in response to the received data.

6. The device of claim 1, wherein the input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture includes

an input circuit configured for receiving data corresponding to a runtime execution of a first instruction associated with an application that is executed by a first processor having a first architecture.

7. The device of claim 1, wherein the input circuit configured for receiving data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture includes

an input circuit configured for receiving data transparent to software executing on the first processor and corresponding to a runtime execution of a first instruction that is executed by the first processor having a first architecture.

8. The device of claim 1, wherein the generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data includes

a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second instruction set architecture in response to the received data.

9. The device of claim 1, wherein the generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data includes

a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction associated by a second processor having a second microarchitecture in response to the received data.

10. The device of claim 1, wherein the generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data includes

a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data, the second instruction being at least substantially similar to the first instruction.

11. The device of claim 1, wherein the generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data includes

a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data, the second instruction being at least substantially different from the first instruction.

12. The device of claim 1, wherein the generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data includes

a generator circuit configured for creating an execution-based optimization profile useable in prefetching data in conjunction with an execution of a second instruction by a second processor having a second architecture in response to the received data.

13. The device of claim 1, wherein the generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data includes

a generator circuit configured for creating an execution-based optimization profile useable in prefetching a third instruction in conjunction with an execution of a second instruction by a second processor having a second architecture in response to the received data.

14. The device of claim 1, wherein the first instruction includes at least one of a machine-level instruction, a compiled instruction, a compilable instruction, one instruction, at least two instructions, an instruction line, an instruction block, an atomic instruction block, a program, and/or an application.

15. The device of claim 1, wherein the first processor includes an x86 architecture.

16. The device of claim 1, wherein the second processor includes an x86 architecture.

17. The device of claim 1, further comprising:

an information store configured by the execution-based optimization profile.

18. The device of claim 1, further comprising:

an output circuit configured for broadcasting the execution-based optimization profile.

19. The device of claim 1, further comprising:

an execution modification circuit configured for modifying an execution of the second instruction in response to the execution-based optimization profile.

20. The device of claim 1, wherein the generator circuit is further configured to:

compare the runtime execution of the first instruction pursuant to a first resource management policy with a second runtime execution of the first instruction pursuant to a second resource management policy, the first resource management policy being an optimistic policy that assumes that the first instruction will execute in a substantially optimal manner, and the second resource management policy being a pessimistic policy that assumes that the first instruction will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the first instruction;

based at least partially on the comparison, select from the first resource management policy and the second resource management policy a resource management policy likely to provide a substantially optimum execution of the first instruction; and

create the execution-based optimization profile based at least partially on the selected resource management policy.

21. A device comprising:

means for receiving data transparent to software executing on a first processor having a first architecture and corresponding to a runtime execution of a first instruction that is executed by the first processor; and

means for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data.

22. The device of claim 21, further comprising:

means for configuring an information store in response to the execution-based optimization profile.

23. An apparatus comprising:

an input module configured to receive data transparent to software executing on a first processor having a first instruction set architecture and corresponding to a runtime execution of a first instruction that is executed by the first processor; and

a generator module configured to create an execution optimization information useable in an execution of a second instruction by a second processor having a second instruction set architecture in response to the received data.

24. The apparatus of claim 23, wherein the second instruction set architecture of the second processor is at least substantially different from the first instruction set architecture of the first processor, or at least substantially similar to the first instruction set architecture of the first processor.

25. The apparatus of claim 23, further comprising:

a broadcast module configured to encode a computer-readable signal-bearing medium with the execution optimization information.

26. The apparatus of claim 23, further comprising:

a broadcast module configured to transmit a computer-readable signal-bearing medium encoded with the execution optimization information.

27. The apparatus of claim 23, further comprising:

an execution optimization module configured to optimize an execution of the second instruction in response to the execution optimization information.

28. An apparatus comprising:

a receiver module configured to acquire data transparent to software executing on a first processor having a first microarchitecture and corresponding to a runtime execution of a first instruction that is executed by the first processor; and

a generator module configured to create an execution optimization information useable in an execution of a second instruction by a second processor having a second microarchitecture in response to the acquired data.

29. The apparatus of claim 28, wherein the second microarchitecture of the second processor is at least substantially different from the first microarchitecture of the first processor or at least substantially similar to the first microarchitecture of the first processor.

30. The apparatus of claim 28, further comprising:

an execution optimization module configured to optimize an execution of the second instruction in response to the execution optimization information.

31. A method implemented at least partially by one or more processors, the method comprising:

receiving hardware-gathered data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture; and

creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture in response to the received hardware-gathered data.

32. The method of claim 31, wherein the receiving hardware-gathered data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture includes

receiving hardware-gathered data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first instruction set architecture.

33. The method of claim 31, wherein the receiving hardware-gathered data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first architecture includes

receiving hardware-gathered data corresponding to a runtime execution of a first instruction that is executed by a first processor having a first microarchitecture.

34. The method of claim 31, wherein the creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture in response to the received hardware-gathered data includes

creating an execution optimization information useable in an execution of a second instruction by a second processor having a second instruction set architecture in response to the received hardware-gathered data.

35. The method of claim 31, wherein the creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture in response to the received hardware-gathered data includes

creating an execution optimization information useable in an execution of a second instruction by a second processor having a second microarchitecture in response to the received hardware-gathered data.

36. The method of claim 31, further comprising:

saving the execution optimization information.

37. The method of claim 31, further comprising:

marketing the execution optimization information.

38. The method of claim 31, further comprising:

facilitating entry of the execution optimization information into a stream of commerce.

39. The method of claim 31, further comprising:

encoding a computer-readable signal-bearing medium with the execution optimization information.

40. The method of claim 39, further comprising:

broadcasting the computer-readable signal-bearing medium encoded with the execution optimization information.

41. The method of claim 31, further comprising:

modifying an execution of the second instruction in response to the execution optimization information.

42. A computer program product comprising:

an article of manufacture including a signal-bearing storage medium bearing an execution-based optimization profile usable during an execution of a computer program by a second processor having a second architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program that is executed by a first processor having a first architecture.

43. The computer program product of claim 42, wherein the execution-based optimization profile usable during an execution of a computer program by a second processor having a second architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program that is executed by a first processor having a first architecture includes

an execution-based optimization profile usable during an execution of a computer program by a second processor having a second instruction set architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program that is executed by a first processor having a first instruction set architecture.

44. The computer program product of claim 42, wherein the execution-based optimization profile usable during an execution of a computer program by a second processor having a second architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program that is executed by a first processor having a first architecture includes

an execution-based optimization profile usable during an execution of a computer program by a second processor having a second microarchitecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program that is executed by a first processor having a first microarchitecture.

45. The computer program product of claim 42, wherein the signal-bearing storage medium includes a transportable computer storage medium.

46. The computer program product of claim 42, wherein the signal-bearing storage medium includes a portable computer storage medium.

47. The computer program product of claim 42, wherein an execution of the computer program by the second processor is modifiable in response to the execution-based optimization profile.

48. A device comprising:

a first processor having a first architecture, the first processor configured to perform a runtime execution of a first instruction;

an input circuit configured for collecting data corresponding to the runtime execution of the first instruction by the first processor having the first architecture from a communications link exposed to the first processor; and

a generator circuit configured for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the collected data,

wherein the second processor having the second architecture is included as at least part of another device.

49. The device of claim 48, wherein the input circuit configured for collecting data corresponding to the runtime execution of the first instruction by the first processor having the first architecture from a communications link exposed to the first processor includes

an input circuit configured for collecting data corresponding to the runtime execution of the first instruction by the first processor having the first architecture from a communications link exposed to the first processor in a manner that is transparent to software executing on the first processor, the software executing on the first processor including the first instruction.

50. The device of claim 48, wherein the input circuit configured for collecting data corresponding to the runtime execution of the first instruction by the first processor having the first architecture from a communications link exposed to the first processor includes

an input circuit configured for collecting data that is derived from the runtime execution of the first instruction by the first processor having the first architecture from a communications link exposed to the first processor.

51. The device of claim 48, wherein the input circuit configured for collecting data corresponding to the runtime execution of the first instruction by the first processor having the first architecture from a communications link exposed to the first processor includes

an input circuit configured for collecting data that is responsive to the runtime execution of the first instruction by the first processor having the first architecture from a communications link exposed to the first processor at least partially while software is executing on the first processor, the software executing on the first processor including the first instruction.

52. The device of claim 48, further comprising:

an output circuit configured for broadcasting the execution-based optimization profile to at least the other device that includes the second processor having the second architecture.