Non-volatile memory system storing data in single-level cell or multi-level cell according to data characteristics

• US 8,214,582 B2
• Filed: 02/24/2010
• Issued: 07/03/2012
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Yang-sup, Talawar, Prakash, Park, Chan-ik
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US12/711,461
• Publication Number:
  US 20100153632A1
• Time in Patent Office: 860 Days
• Field of Search: 711/103, 365/63
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics. The non-volatile memory system includes a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area, and an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal. A flash transition layer receives the data characteristic signal, and determines whether the write data should be stored in the MLC area or the SLC area based on whether or not the write data will be accessed by the file, or whether the address associated with the write data is frequently updated or not.

Claims

1. A non-volatile memory system comprising:

a non-volatile memory cell array having a plurality of multi-level cells forming a first area and a plurality of single-level cells forming a second area and configured to store write data at one of the first area and the second area; and

a flash transition layer (FTL) configured to determine whether the write data should be stored in the first area or the second area based on a write data characteristic signal defined by an update characteristic of the write data,

wherein the update characteristic of the write data is the number of access of an address associated with the write data,

the FTL comprises a plurality of entries including at least one store entry and at least one empty entry,

the FTL stores the number of access of the address to the empty entry, if there is no store entry corresponding to the address, and the FTL stores the number of access to the store entry selected in response to a least recently used (LRU) value, if there is no store entry corresponding to the address and no empty entry.

2. The system of claim 1, wherein the FTL stores the number of access of the address to the store entry, if there is the store entry allocated to the address.

3. The system of claim 1, wherein each store entry is allocated to a corresponding address of the write data.

4. The system of claim 1, wherein each entry is included in a data block history storage.

5. The system of claim 1, wherein each entry further stores the LRU value.

6. The system of claim 1, wherein the FTL generates the write data characteristic signal.

7. The system of claim 1, wherein write data characteristic signal is received from the at least one of an application and a file system.