Memory controller device having timing offset capability

• US 8,214,616 B2
• Filed: 05/29/2007
• Issued: 07/03/2012
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US11/754,995
• Publication Number:
  US 20070255919A1
• Time in Patent Office: 1,862 Days
• Field of Search: None
• US Class Current: 711/167
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data suing a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.

Claims

1. A memory system comprising:

a memory controller component;

a plurality of memory components including a first memory component and a second memory component;

conductors coupling the memory controller component to the plurality of memory components, wherein the conductors comprise;

a common address/control bus connecting the memory controller component to each of the memory components in succession such that a first propagation time required for signals indicative of a write operation to propagate on the address/control bus from the memory controller component to the first memory component is different than a second propagation time required for the signals indicative of the write operation to propagate on the address/control bus from the memory controller component to the second memory component;

separate first and second data buses connecting the memory controller component to the first and second memory components, the first data bus to convey first data, associated with the write operation, to the first memory component, and the second data bus to convey second data, associated with the write operation, to the second memory component;

first and second timing signal conductors that extend from the memory controller component to the first and second memory components, respectively, the first timing signal conductor to convey a first timing signal that controls a time at which the first memory component samples the first data and the second timing signal conductor to convey a second timing signal that controls a time at which the second memory component samples the second data; and

wherein the memory controller component includes circuitry to offset phases of the first and second timing signals based, at least in part, on the difference between the first and second propagation times.

2. The memory system of claim 1 wherein the signals indicative of a write operation propagate past the first memory component before reaching the second memory component.

3. The memory system of claim 1 wherein the first and second timing signal conductors are disposed substantially parallel to the first and second data buses, respectively, such that the first timing signal propagating on the first timing signal conductor tracks the first data propagating on the first data bus, and the second timing signal propagating on the second timing signal conductor tracks the second data propagating on the second data bus.

4. The memory system of claim 3 wherein the first timing signal propagates at substantially the same speed and in substantially the same direction as the first data, and wherein the second timing signal propagates at substantially the same speed and in substantially the same direction as the second data.

5. The memory system of claim 1 wherein the conductors coupling the memory controller component to the plurality of memory components further comprises a third timing signal conductor that extends from the memory controller component to the first and second memory components in succession such that a time required for a third timing signal to propagate on the third timing signal conductor from the memory controller component to the first memory component is substantially equal to the first propagation time, and a time required for the third timing signal to propagate on the third timing signal conductor from the memory controller component to the second memory component is substantially equal to the second propagation time.

6. The memory system of claim 5 wherein the third timing signal controls a time at which the first and second memory components sample the signals indicative of a write operation.

7. The memory system of claim 5 wherein the third timing signal conductor is disposed substantially parallel to the common address/control bus such that the third timing signal propagating on the third timing signal conductor tracks a signal indicative of a write operation propagating on the common address/control bus.

8. The memory system of claim 7 wherein the third timing signal propagates past the first memory component before reaching the second memory component.

9. The memory system of claim 5 wherein the first and second timing signals are derived from the third timing signal.

10. The memory system of claim 1 wherein the first and second timing signals are strobe signals.

11. The memory system of claim 1 wherein the memory controller component further comprises circuitry to offset phases of the first and second data propagating on the respective first and second data buses based, at least in part, on the difference between the first and second propagation times.

12. A memory controller for coupling, via conductors, to a plurality of memory components including a first memory component and a second memory component, wherein the conductors include:

a common address/control bus to connect the memory controller component to each of the memory components in succession such that a first propagation time required for signals indicative of a write operation to propagate on the address/control bus from the memory controller component to the first memory component is different than a second propagation time required for the signals indicative of the write operation to propagate on the address/control bus from the memory controller component to the second memory component;

separate first and second data buses to connect the memory controller component to the first and second memory components, the first data bus to convey first data, associated with the write operation, to the first memory component, and the second data bus to convey second data, associated with the write operation, to the second memory component;

first and second timing signal conductors to extend from the memory controller component to the first and second memory components, respectively, the first timing signal conductor to convey a first timing signal that controls a time at which the first memory component samples the first data and the second timing signal conductor to convey a second timing signal that controls a time at which the second memory component samples the second data; and

wherein the memory controller comprises;

circuitry to offset phases of the first and second timing signals based, at least in part, on the difference between the first and second propagation times.

13. The memory controller of claim 12 wherein the signals indicative of a write operation propagate past the first memory component before reaching the second memory component.

14. The memory controller of claim 12 wherein the first and second timing signal conductors are disposed substantially parallel to the first and second data buses, respectively, such that the first timing signal propagating on the first timing signal conductor tracks the first data propagating on the first data bus, and the second timing signal propagating on the second timing signal conductor tracks the second data propagating on the second data bus.

15. The memory controller of claim 14 wherein the first timing signal propagates at substantially the same speed and in substantially the same direction as the first data, and wherein the second timing signal propagates at substantially the same speed and in substantially the same direction as the second data.

16. The memory controller of claim 12 wherein the conductors coupling the memory controller component to the plurality of memory components further comprise a third timing signal conductor that extends from the memory controller component to the first and second memory components to convey a third timing signal that controls a time at which the first and second memory components sample the signals indicative of a write operation.

17. The memory controller of claim 16 wherein the third timing signal conductor is disposed substantially parallel to the common address/control bus such that the third timing signal propagating on the third timing signal conductor tracks a signal indicative of a write operation propagating on the common address/control bus.

18. The memory controller of claim 16 wherein the third timing signal propagates past the first and second memory components in succession such that a time required for the third timing signal to propagate from the memory controller component to the first memory component is substantially equal to the first propagation time, and a time required for the third timing signal to propagate from the memory controller component to the second memory component is substantially equal to the second propagation time.

19. The memory controller of claim 16 wherein the first and second timing signals are derived from the third timing signal.

20. The memory controller of claim 19 wherein the circuitry to offset the phases of the first and second timing signals comprises one or more phase-locked loop (PLL) circuits.

21. The memory controller of claim 12 wherein the memory controller component further comprises circuitry to offset phases of the first and second data propagating on respective first and second data buses based, at least in part, on the difference between the first and second propagation times.

22. A method for conducting memory operations in a memory system comprising:

a memory controller component and a plurality of memory components including a first memory component and a second memory component; and

conductors coupling the memory controller component to the plurality of memory components, wherein the conductors comprise;

a common address/control bus connecting the memory controller component to each of the memory components in succession such that a first propagation time required for signals indicative of a write operation to propagate on the address/control bus from the memory controller component to the first memory component is different than a second propagation time required for the signals indicative of the write operation to propagate on the address/control bus from the memory controller component to the second memory component;

separate first and second data buses connecting the memory controller component to the first and second memory components, the first data bus to convey first data, associated with the write operation, to the first memory component, and the second data bus to convey second data, associated with the write operation, to the second memory component; and

first and second timing signal conductors that extend from the memory controller component to the first and second memory components, respectively, the first timing signal conductor to convey a first timing signal that controls a time at which the first memory component samples the first data and the second timing signal conductor to convey a second timing signal that controls a time at which the second memory component samples the second data;

the method comprising;

offsetting phases of the first and second timing signals based, at least in part, on the difference between the first and second propagation times.

23. The method of claim 22 further comprising deriving the first and second timing signals from a third timing signal that propagates on a third timing signal conductor, wherein the third timing signal conductor is disposed substantially parallel to the common address/control bus such that the third timing signal propagating on the third timing signal conductor tracks a signal indicative of a write operation propagating on the common address/control bus.

24. The method of claim 22 further comprising offsetting the phases of the first and second data propagating on respective first and second data buses based, at least in part, on the difference between the first and second propagation times.

25. A memory controller component comprising:

a clock buffer to transmit a clock signal onto an external clock line routed in succession to a first memory component and a second memory component wherein a first propagation time required for the clock signal to propagate on the clock line from the memory controller component to the first memory component is shorter than a second propagation time required for the clock signal to propagate on the clock line from the memory controller component to the second memory component;

a first circuit to transmit control information from the memory controller component to the first memory component and the second memory component wherein the control information specifies a write operation of first data to the first memory component and second data to the second memory component;

a second circuit to transmit the first data to the first memory component but not the second memory component;

a third circuit to transmit the second data to the second memory component but not the first memory component;

a fourth circuit to transmit a first timing signal to the first memory component but not the second memory component, wherein the first memory component uses the first timing signal to sample the first data;

a fifth circuit to transmit a second timing signal to the second memory component but not the first memory component, wherein the second memory component uses the second timing signal to sample the second data; and

wherein phases of the first and second timing signals are offset based, at least in part, on the difference between the first and second propagation times.

26. The memory controller of claim 25, wherein the first timing signal is a first strobe signal and the second timing signal is a second strobe signal.

27. The memory controller component of claim 26, further comprising circuitry to offset transmit phases of the first data and the second data based, at least in part, on the difference between the first and second propagation times.

28. The memory controller of claim 27, further comprising clock generation circuitry to generate a plurality of phase-distributed clock signals and an internal clock signal, the plurality of phase-distributed clock signals having phase offsets that are substantially evenly distributed within a cycle time of the internal clock signal, wherein the circuitry to offset transmit phases of the first data and the second data uses clock signals selected from the plurality of phase-distributed clock signals to offset transmit phases of the first data and the second data.

29. The memory controller of claim 28, wherein the clock generation circuitry comprises a phase-locked loop circuit to generate the internal clock signal based on a reference clock signal that has a lower frequency than the internal clock signal.

30. The memory controller component of claim 28, wherein the circuitry to offset the transmit phases of the first data and the second data includes a plurality of phase offset selection circuits, wherein a first phase offset selection circuit of the plurality of phase offset selection circuits selects a first phase-distributed clock signal from the plurality of phase-distributed clock signals to be a timing reference for transmission of the first data and a second phase offset selection circuit of the plurality of phase offset selection circuits selects a second phase-distributed clock signal from the plurality of phase-distributed clock signals to be a timing reference for transmission of the second data.

31. The memory controller of claim 30, wherein the first phase offset selection circuit comprises a multiplexer to select the first phase-distributed clock signal and the second phase offset selection circuit comprises a multiplexer to select the second phase-distributed clock signal.

32. The memory controller component of claim 28, wherein the circuitry to offset the transmit phases of the first data and the second data includes a plurality of phase offset selection circuits, each phase offset selection circuit of the plurality of phase offset selection circuits including a phase interpolator to interpolate between two phase-distributed clock signals of the plurality of phase-distributed clock signals and generate a signal to be a timing reference for transmission of the respective first data and the second data.

33. The memory controller component of claim 25, wherein a difference between the first and second propagation times exceeds a period of the clock signal.

34. The memory controller component of claim 25, wherein:

the first timing signal is transmitted such that the propagation of the first timing signal to the first memory component tracks the propagation of the first data as the first data is transmitted from the memory controller component to the first memory component; and

the second timing signal is transmitted such that the propagation of the second timing signal to the second memory component tracks the propagation of the second data as the second data is transmitted from the memory controller component to the second memory component.

35. The memory controller component of claim 25, wherein the clock signal is transmitted such that the propagation of the clock signal, as the clock signal traverses the external clock line, tracks the propagation of the control information as the control information propagates from the memory controller component to the first memory component and the second memory component.

36. A memory controller component comprising:

a clock buffer to provide a clock signal to an external clock line routed in succession to a first and second memory component, wherein a first propagation time required for the clock signal to propagate on the clock line from the memory controller component to the first memory component is shorter than a second propagation time required for the clock signal to propagate on the clock line from the memory controller component to the second memory component;

a first transmitter to transmit first data along a first dedicated data bus to the first memory component;

a second transmitter to transmit second data along a second dedicated data bus to the second memory component wherein a time at which the second data is transmitted is offset from a time at which the first data is transmitted based, at least in part, on the difference between the first and second propagation times;

a third transmitter to transmit a first strobe signal along a first dedicated strobe signal line to the first memory component, wherein the first memory component receives the first strobe signal to sample the first data;

a fourth transmitter to transmit a second strobe signal along a second dedicated strobe signal line to the second memory component, wherein the second memory component receives the second strobe signal to sample the second data, wherein a time at which the second strobe signal is transmitted is offset from a time at which the first strobe signal is transmitted based, at least in part, on the difference between the first and second propagation times.

37. The memory controller of claim 36, further comprising clock generation circuitry to generate a plurality of phase-distributed clock signals, the plurality of phase-distributed clock signals having phase offsets that are substantially evenly distributed within a cycle time of an internal clock signal, wherein a clock signal used to time transmission of the second data is generated using the plurality of phase-distributed clock signals.

38. The memory controller component of claim 37, wherein the clock signal used to time transmission of the second data is phase interpolated from a pair of clock signals selected from the plurality of phase-distributed clock signals, based on the difference between the first and second propagation times.

39. The memory controller of claim 37, further comprising a multiplexer to select a clock signal of the plurality of phase distributed clock signals to be the clock signal used to time the transmission of the second data.

40. The memory controller of claim 37, wherein the clock generation circuitry comprises a phase-locked loop circuit to generate the internal clock signal based on a reference clock signal that has a lower frequency than the internal clock signal, wherein the phase locked loop circuit includes a chain of buffers including a buffer to provide the internal clock signal, each buffer of the chain of buffers to provide a respective clock signal of the plurality of phase distributed clock signals.

41. The memory controller component of claim 36, wherein the time at which the second data is transmitted is offset from the time at which the first data is transmitted to compensate for the difference between the first and second propagation times.

42. The memory controller component of claim 36, wherein a difference between the first and second propagation times exceeds a period of the clock signal.

43. The memory controller component of claim 42, wherein each bit of the control information is valid at an input of each of the first and second memory component for bit time intervals that each correspond to a predetermined fraction of the period of the clock signal.

44. The memory controller component of claim 36, wherein:

the first strobe signal is transmitted such that the propagation of the first strobe signal to the first memory component tracks the propagation of the first data as the first data is transmitted from the memory controller component to the first memory component; and

the second strobe signal is transmitted such that the propagation of the second strobe signal to the second memory component tracks the propagation of the second data as the second data is transmitted from the memory controller component to the second memory component.

45. The memory controller component of claim 36, further comprising a circuit to transmit control information from the memory controller component to the first memory component and the second memory component wherein the control information specifies a write operation of the first data to the first memory component and the second data to the second memory component, wherein the clock signal is transmitted such that the propagation of the clock signal, as the clock signal traverses the external clock line, tracks the propagation of the control information as the control information propagates from the memory controller component to the first memory component and the second memory component.

46. The memory controller component of claim 45, wherein the memory controller includes a circuit to transmit address information, associated with the write operation, such that a propagation time required for the address information to propagate from the memory controller component to the first memory component tracks the first propagation time required for the clock signal to propagate from the memory controller component to the first memory component, and a propagation time required for the address information to propagate from the first memory component to the second memory component tracks a propagation time required for the clock signal to propagate from the first memory component to the second memory component.

47. The memory controller component of claim 45, wherein the circuit to transmit control information and the circuit to transmit address information are included in an address/control transmit block.

48. The memory controller component of claim 47, wherein the circuit to transmit control information includes a driver to output at least a first bit of the control information to an external control bus.

49. A memory controller component comprising:

a clock buffer to provide a clock signal to an external clock line routed in succession to a first and second memory component, wherein a first propagation time required for the clock signal to propagate on the clock line from the memory controller component to the first memory component is shorter than a second propagation time required for the clock signal to propagate on the clock line from the memory controller component to the second memory component;

a circuit to convey address and control (AC) information from the memory controller component to the first memory component and the second memory component, wherein the AC information specifies a write operation of first data to the first memory component and second data to the second memory component, wherein a time that a bit of the AC information takes to propagate from the memory controller component to the first memory component tracks the first propagation time, and a time that the bit takes to propagate from the memory controller component to the second memory component substantially tracks the second propagation time;

a first transmitter to transmit the first data to the first memory component;

a second transmitter to transmit the second data to the second memory component wherein a time at which the second data is transmitted is offset from a time at which the first data is transmitted based, at least in part, on the difference between the first and second propagation times;

a third transmitter to transmit a first strobe signal to the first memory component, wherein the first memory component receives the first strobe signal to sample the first data, wherein the first strobe signal is transmitted such that the propagation of the first strobe signal to the first memory component tracks the propagation of the first data as the first data is transmitted from the memory controller component to the first memory component; and

a fourth transmitter to transmit a second strobe signal to the second memory component, wherein the second memory component receives the second strobe signal to sample the second data, wherein a time at which the second strobe signal is transmitted is offset from a time at which the first strobe signal is transmitted based, at least in part, on the difference between the first and second propagation times, wherein the second strobe signal is transmitted such that the propagation of the second strobe signal to the second memory component tracks the propagation of the second data as the second data is transmitted from the memory controller component to the second memory component.

50. A method of operation in a memory controller component, the method comprising:

providing a clock signal onto an external clock line routed in succession to a first and second memory component, wherein a first propagation time required for the clock signal to propagate on the clock line from the memory controller component to the first memory component is shorter than a second propagation time required for the clock signal to propagate on the clock line from the memory controller component to the second memory component;

providing control information to the first memory component and the second memory component, wherein the control information specifies a write operation of first data to the first memory component and second data to the second memory component;

transmitting the first data along a first dedicated data bus to the first memory component;

transmitting the second data along a second dedicated data bus to the second memory component;

transmitting a first timing signal to the first memory component, wherein the first memory component receives the first timing signal to sample the first data;

transmitting a second timing signal to the second memory component, wherein the second memory component receives the second timing signal to sample the second data; and

offsetting the phase of the first timing signal from the phase of the second timing signal based, at least in part, on the difference between the first and second propagation times.

51. The method of claim 50, wherein the first timing signal is a first strobe signal and the second timing signal is a second strobe signal.

52. The method of claim 50, further comprising phase interpolating from a pair of clock signals selected from a plurality of phase distributed clock signals to generate a clock signal used to time the transmitting of the first data.

53. The method of claim 50, wherein:

transmitting the first timing signal further comprises transmitting the first timing signal such that the propagation of the first timing signal to the first memory component tracks the propagation of the first data as the first data is transmitted from the memory controller component to the first memory component; and

transmitting the second timing signal further comprises transmitting the second timing signal such that the propagation of the second timing signal to the second memory component, tracks the propagation of the second data as the second data is transmitted from the memory controller component to the second memory component.

54. The method of claim 50, wherein transmitting control information further comprises transmitting the control information such that the propagation of the clock signal, as the clock signal traverses the external clock line, tracks the propagation of the control information as the control information propagates from the memory controller component to the first memory component and the second memory component.

55. The method of claim 50, further comprising transmitting address information, associated with the write operation, such that a propagation time required for the address information to propagate from the memory controller component to the first memory component tracks the first propagation time required for the clock signal to propagate from the memory controller component to the first memory component, and a propagation time required for the address information to propagate from the first memory component to the second memory component tracks a propagation time required for the clock signal to propagate from the first memory component to the second memory component.