Non-volatile memory and method with post-write read and adaptive re-write to manage errors

• US 8,214,700 B2
• Filed: 10/28/2009
• Issued: 07/03/2012
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Chen, Jian
• Primary Examiner(s): Maskulinski, Michael
• Application Number:
  US12/607,522
• Publication Number:
  US 20110099418A1
• Time in Patent Office: 979 Days
• Field of Search: None
• US Class Current: 714/721
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used.

Claims

1. A method of operating a non-volatile memory, comprising:

configuring the memory into first and second portions, the first portion having memory cells operating with a margin of error larger than that of the second portion;

programming a first copy of a group of input data into the second portion;

reading the first copy from the second portion to check for error after a predefined time; and

if the error in the first copy is less than a predetermined number of error bits, identifying the first copy as valid data in subsequent read operations;

otherwise

programming a second copy of the group of input data into the first portion and identifying the second copy as valid data in subsequent read operations.

2. The method as in claim 1, further comprising:

providing first and second sections in the first portion, the first section for caching input data, and the second section for rewriting a second copy of the group of data after the error in first copy is found to exceed the predetermined number of error bits;

programming a cached copy of the input data to the first section; and

wherein said programming of the second copy is based on the cached copy and is into the second section of the first portion.

3. The method as in claim 1, wherein:

the memory is formed on an integrated circuit chip with a set of data latches; and

said reading the first copy to check for errors further comprises;

reading the first copy and the cached copy to the set of data latches; and

comparing the first copy and the cached copy at the set of data latches.

4. The method as in claim 1, wherein:

the predefined time is the completion of programming of neighboring memory cells that may significantly perturb the group of input data.

5. The method as in claim 1, wherein:

the predefined time is the completion of programming all memory cells in the block containing the group of input data.

6. The method as in claim 1, further comprising:

providing an ECC for correcting at least the predetermined amount of error.

7. The method as in claims 1, further comprising:

providing an ECC for correcting a number of error bits significantly greater than the predetermined number of error bits.

8. A method of operating a non-volatile memory, comprising:

configuring the memory into first and second portions, the first portion having memory cells operating with a margin of error larger than that of the second portion and for caching input data;

programming a cached copy of a group of input data into the first portion;

programming a first copy of the group of input data into the second portion;

reading the first copy from the second portion to check for error after a predefined time; and

if the error in the first copy is less than a predetermined number of error bits, identifying the first copy as valid data in subsequent read operations;

otherwise

identifying the cached copy as valid data in subsequent read operations.

9. The method as in claim 8, wherein:

the memory is formed on an integrated circuit chip with a set of data latches; and

said reading the first copy to check for errors further comprises;

reading the first copy and the cached copy to the set of data latches; and

comparing the first copy and the cached copy at the set of data latches.

10. The method as in claim 8, wherein:

the predefined time is the completion of programming of neighboring memory cells that may significantly perturb the group of input data.

11. A memory, comprising:

an array of non-volatile memory cells having first and second portions, the first portion having memory cells operating with a margin of error larger than that of the second portion;

a controller for controlling operations of the memory, said operations including;

programming a first copy of a group of input data into the second portion;

reading the first copy from the second portion to check for error after a predefined time; and

if the error in the first copy is less than a predetermined number of error bits, identifying the first copy as valid data in subsequent read operations;

otherwise

programming a second copy of the group of input data into the first portion and identifying the second copy as valid data in subsequent read operations.

12. The memory as in claim 11, further comprising:

first and second sections in the first portion, the first section for caching input data, and the second section for rewriting a second copy of the group of data after the error in first copy is found to exceed the predetermined number of error bits; and

wherein said operations further includes;

programming a cached copy of the input data to the first section; and

wherein said programming of the second copy is based on the cached copy and is into the second section of the first portion.

13. The memory as in claim 11, wherein:

the memory is formed on an integrated circuit chip with a set of data latches; and

said operation of reading the first copy to check for errors further comprises;

reading the first copy and the cached copy to the set of data latches; and

comparing the first copy and the cached copy at the set of data latches.

14. The memory as in claim 11, wherein:

the predefined time is the completion of programming of neighboring memory cells that may significantly perturb the group of input data.

15. The memory as in claim 11, wherein:

the predefined time is the completion of programming all memory cells in the block containing the group of input data.

16. The memory as in claim 11, further comprising:

an ECC for correcting at least the predetermined amount of error.

17. The memory as in claims 11, further comprising:

an ECC for correcting a number of error bits significantly greater than the predetermined number of error bits.

18. A memory, comprising:

an array of non-volatile memory cells having first and second portions, the first portion having memory cells operating with a margin of error larger than that of the second portion and for caching input data;

a controller for controlling operations of the memory, said operations including;

programming a cached copy of a group of input data into the first portion;

programming a first copy of the group of input data into the second portion;

reading the first copy from the second portion to check for error after a predefined time; and

if the error in the first copy is less than a predetermined number of error bits, identifying the first copy as valid data in subsequent read operations;

otherwise

identifying the cached copy as valid data in subsequent read operations.

19. The memory as in claim 18, wherein:

the memory is formed on an integrated circuit chip with a set of data latches; and

said operation of reading the first copy to check for errors further comprises;

reading the first copy and the cached copy to the set of data latches; and

comparing the first copy and the cached copy at the set of data latches.

20. The memory as in claim 18, wherein:

the predefined time is the completion of programming of neighboring memory cells that may significantly perturb the group of input data.