Model import for electronic design automation

• US 8,214,772 B2
• Filed: 05/26/2011
• Issued: 07/03/2012
• Est. Priority Date: 05/15/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ru-Gun, Lai, Chih-Ming, Huang, Wen-Chun, Luo, Boren, Shin, I-Chang, Ku, Yao-Ching, Hou, Cliff
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/116,981
• Publication Number:
  US 20110231804A1
• Time in Patent Office: 404 Days
• Field of Search: 716/52, 716/54, 430/5, 382/144
• US Class Current: 716/52
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]

Abstract

Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Claims

1. A method, comprising:

providing a set of processing parameters from a fabrication facility;

creating a model from the set of processing parameters, the model being in the form of electronic data;

using a processor for;

converting the model into a corresponding set of kernels;

converting the set of kernels into a corresponding set of matrices;

creating hot spot detection rules and hot spot correction rules based on the set of processing parameters;

communicating the set of matrices, the hot spot detection rules, and the hot spot correction rules to a design facility; and

wherein the set of matrices, the hot spot detection rules, and the hot spot correction rules are adapted for use with a plurality of EDA tools.

2. The method of claim 1, wherein the design facility is positioned remotely from the fabrication facility.

3. The method of claim 1, wherein the hot spot detection rules include a minimum density rule for interconnects in a circuit layout.

4. The method of claim 1, wherein the hot spot correction rules include guidance parameters designed to guide the modification of a circuit layout when the circuit layout violates the hot spot detection rules.

5. The method of claim 1, wherein the hot spot detection rules include rules to detect in a circuit layout the potential for at least one of pinching, bridging, dishing, erosion, RC delay, metal line thickness variations, and Cu residue.

6. The method of claim 1, wherein the hot spot correction rules include rules to correct a circuit layout to prevent at least one of pinching, bridging, dishing, erosion, RC delay, metal line thickness variations, and Cu residue.

7. In a data processing system, a method for providing semiconductor fabrication processing parameters to a design facility, the method comprising:

providing a set of semiconductor processing parameters from a fabrication facility to an input of a processor;

the processor establishing a processing model based on the set of semiconductor processing parameters;

the processor creating hot spot detection rules and hot spot correction rules based on the set of semiconductor processing parameters;

the processor converting the processing model into a set of kernels; and

an output of the processor sending the set of kernels to the design facility in a format that can be used with a first electronic design automation (EDA) tool.

8. The method of claim 7, wherein the sending includes:

extracting a set of matrices from the set of kernels; and

sending the set of matrices to the design facility.

9. The method of claim 7, further comprising the output of the processor communicating the hot spot detection rules and the hot spot correction rules to the design facility.

10. The method of claim 9, wherein the communicating includes transmitting the hot spot detection rules and the hot spot correction rules to the design facility over an encrypted communication channel.

11. The method of claim 7, wherein the sending is carried out in a manner so that the set of kernels have a format that can be used with a second EDA tool, the second EDA tool being different from the first EDA tool.

12. The method of claim 7, further comprising sending the set of kernels, the hot spot detection rules, and the hot spot correction rules to a plurality of design facilities over a computer network.

13. The method of claim 7, wherein the hot spot correction rules include guidance parameters designed to guide the modification of a circuit layout when the circuit layout violates the hot spot detection rules.

14. The method of claim 7, wherein the hot spot detection rules include rules to detect in a circuit layout the potential for at least one of pinching, bridging, dishing, erosion, RC delay, metal line thickness variations, and Cu residue.

15. The method of claim 7, wherein the hot spot correction rules include rules to correct a circuit layout to prevent at least one of pinching, bridging, dishing, erosion, RC delay, metal line thickness variations, and Cu residue.

16. In a data processing system, a method for providing semiconductor fabrication processing parameters to a design entity, the method comprising:

providing a set of processing parameters from a fabrication entity to an input of a processor;

the processor creating a processing model from the set of semiconductor processing parameters;

the processor creating hot spot detection rules and hot spot correction rules based on the set of semiconductor processing parameters;

the processor converting the processing model into a set of two-dimensional kernels;

the processor converting the set of two-dimensional kernels into a set of matrices, the set of matrices being in a format recognizable by an electronic design automation (EDA) tool; and

an output of the processor communicating the set of matrices to the design entity.

17. The method of claim 16, further comprising the output of the processor communicating the hot spot detection rules and the hot spot correction rules to the design entity.

18. The method of claim 16, wherein the hot spot correction rules include guidance parameters designed to guide the modification of a circuit layout when the circuit layout violates the hot spot detection rules.

19. The method of claim 16, wherein the hot spot detection rules include rules to detect in a circuit layout the potential for at least one of pinching, bridging, dishing, erosion, RC delay, metal line thickness variations, and Cu residue.

20. The method of claim 16, wherein the hot spot correction rules include rules to correct a circuit layout to prevent at least one of pinching, bridging, dishing, erosion, RC delay, metal line thickness variations, and Cu residue.