Stage evaluation of a state machine

• US 8,214,783 B2
• Filed: 05/13/2011
• Issued: 07/03/2012
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: The MathWorks, Inc.
• Original Assignee: The MathWorks, Inc.
• Inventors: Raghavan, Vijay, Mestchian, Ebrahim Mehran
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/106,951
• Publication Number:
  US 20110219350A1
• Time in Patent Office: 417 Days
• Field of Search: 716/100, 716/106, 716/108, 716/136
• US Class Current: 716/106
• CPC Class Codes: G06F 8/10 Requirements analysis; Specification techniques

Abstract

The present invention provides a method and system for stage evaluation of a state machine model. Two types of transitions are used: first-stage transitions and second-stage transitions for a two-stage evaluation. In one embodiment, top-down processing and bottom-up processing may be combined using a two-stage evaluation. First-stage transitions are used with top-down processing while second-stage transitions are used with bottom-up processing. Certain conditions are used to determine if a switch from one type of stage processing to another type of stage processing is needed.

Claims

1. A computing device implemented method comprising:

providing, using the computing device, a representation of a state machine including a plurality of states organized in a hierarchy, the plurality of states interconnected via one or more transitions;

processing the state machine using multiple-stage processing, wherein;

the multiple-stage processing includes a first processing stage and a second processing stage,

the one or more transitions of the state machine include one or more first type transitions and one or more second type transitions, and

the processing is performed using a computing device;

processing valid first type transitions during the first processing stage, the first processing stage processing a first type transition irrespective of the hierarchy; and

processing valid second type transitions during the second processing stage, the second processing stage processing the one or more second type transitions irrespective of the hierarchy.

2. The method of claim 1, wherein the first processing stage ignores one or more second type transitions.

3. The method of claim 1, wherein the second processing stage ignores one or more first type transitions.

4. The method of claim 1, wherein the state machine is a finite state machine.

5. The method of claim 1, wherein the first type of transitions are early transitions and the second type of transitions are late transitions.

6. The method of claim 1, wherein the plurality of the states of the state machine include one or more superstates and one or more substates, a superstate being higher in the hierarchy than a substate.

7. The method of claim 6, wherein the multiple-stage processing includes a third processing stage for processing one or more third type transitions irrespective of the hierarchy.

8. The method of claim 7, wherein:

a transition is processed by the first processing stage when the transition is for executing by a source state of the transition without considering substates of the source state,

the transition is processed by the second processing stage if no valid transitions exist from any immediate substates of the source state, and

the transition is processed by the third processing stage if no valid transitions exist from any of the substates of the source state.

9. In a computing device, a computer readable medium for storing executable instructions for processing a state machine, the medium comprising one or more instructions for:

providing, using the computing device, a representation of a state machine including a plurality of states organized in a hierarchy, the plurality of states interconnected via one or more transitions;

processing the state machine using multiple-stage processing, wherein;

the multiple-stage processing includes a first processing stage and a second processing stage,

the one or more transitions of the state machine include one or more first type transitions and one or more second type transitions, and

the processing is performed using a computing device;

processing valid first type transitions during the first processing stage, the first processing stage processing a first type transition irrespective of the hierarchy; and

processing valid second type transitions during the second processing stage, the second processing stage processing the one or more second type transitions irrespective of the hierarchy.

10. The medium of claim 9, wherein the first processing stage ignores one or more second type transitions.

11. The medium of claim 9, wherein the second processing stage ignores one or more first type transitions.

12. The medium of claim 9, wherein the state machine is a finite state machine.

13. The medium of claim 9, wherein the first type of transitions are early transitions and the second type of transitions are late transitions.

14. The medium of claim 9, wherein the plurality of the states of the state machine include one or more superstates and one or more substates, a superstate being higher in the hierarchy than a substate.

15. The medium of claim 14, wherein the multiple-stage processing includes a third processing stage for processing one or more third type transitions irrespective of the hierarchy.

16. The medium of claim 15, wherein:

a transition is processed by the first processing stage when the transition is for executing by a source state of the transition without considering substates of the source state,

the transition is processed by the second processing stage if no valid transitions exist from any immediate substates of the source state, and

the transition is processed by the third processing stage if no valid transitions exist from any of the substates of the source state.

17. A system comprising:

a storage for storing a representation of a computer implemented state machine including a plurality of states organized in a hierarchy, the plurality of states interconnected via one or more transitions; and

a processor for;

processing the state machine using multiple-stage processing, wherein;

the multiple-stage processing includes a first processing stage and a second processing stage,

the one or more transitions of the state machine include one or more first type transitions and one or more second type transitions, and

the processing is performed using a computing device;

processing valid first type transitions during the first processing stage, the first processing stage processing a first type transition irrespective of the hierarchy; and

processing valid second type transitions during the second processing stage, the second processing stage processing the one or more second type transitions irrespective of the hierarchy.

18. The system of claim 17, wherein the plurality of the states of the state machine includes one or more superstates and one or more substates, a superstate being higher in the hierarchy than a substate.

19. The system of claim 17, wherein the multiple-stage processing includes a third processing stage for processing one or more third type transitions irrespective of the hierarchy.

20. The system of claim 17:

a transition is processed by the first processing stage when the transition is for executing by a source state of the transition without considering substates of the source state,

the transition is processed by the second processing stage if no valid transitions exist from any immediate substates of the source state, and

the transition is processed by the third processing stage if no valid transitions exist from any of the substates of the source state.