Accurate parasitic capacitance extraction for ultra large scale integrated circuits

• US 8,214,784 B2
• Filed: 09/29/2010
• Issued: 07/03/2012
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Ke-Ying, Ho, Chia-Ming, Chang, Gwan Sin, Chen, Chien-Wen
• Primary Examiner(s): Levin, Naum
• Application Number:
  US12/893,870
• Publication Number:
  US 20110023003A1
• Time in Patent Office: 643 Days
• Field of Search: 716110-112, 716/115, 716/136
• US Class Current: 716/110
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Claims

1. A method of conducting testing and simulation, the method comprising:

creating a technology file;

processing the geometry of an integrated circuit layout; and

using an extraction system, extracting parasitic capacitance by pattern-matching a connector configuration in said technology file from a pattern in said integrated circuit layout;

wherein said technology file includes a capacitance table;

wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and

wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance value of an actual connector configuration in an integrated circuit (IC), said actual connector configuration comprising a contact, a via, or a combination thereof.

2. The method of claim 1 further comprising:

reading the technology file into said extraction system; and

reading the integrated circuit layout into said extraction system.

3. The method of claim 2, wherein said each element of said effective connector table has a polygon-shaped connector.

4. The method of claim 3, wherein said each element in said effective connector area table is represented by a width of a square-shaped connector.

5. The method of claim 2, wherein said effective connector area table includes an effective via area table corresponding to vias between two different interconnect layers in said IC.

6. The method of claim 2, wherein said technology file further includes capacitance and resistance of primitives other than contact and via.

7. The method of claim 2, wherein said technology file further includes process and technology parameters.

8. The method of claim 2 further comprising pattern-matching a geometry of said circuit layout to a corresponding element of said capacitance table.

9. The method of claim 8 further comprising retrieving said element of said capacitance table.

10. The method of claim 2 further comprising interpolating or extrapolating an absent connector capacitance based on a geometry of said circuit layout and on said capacitance table.

11. The method of claim 2 further comprising extracting a parasitic capacitance of said circuit layout based on said technology file.

12. The method of claim 2 further comprising forming said actual connector configuration in a semiconductor substrate.

13. The method of claim 1, wherein said creating said technology file includes:

providing connector capacitance test structures, having substantially similar dimensions and different connector configurations;

measuring a parasitic connector capacitance on each of said connector capacitance test structures;

creating an effective connector width table, wherein each element of said effective connector width table corresponds to a polygon-shaped connector and has a calculated parasitic capacitance matching to a measured parasitic capacitance of one of said connector capacitance test structures; and

generating a capacitance table corresponding to said effective connector width table.

14. The method of claim 13, wherein said creating said effective connector width table includes:

providing said measured parasitic capacitance;

preparing a process characterization file, said process characterization file including a trial value of a connector area;

calculating a connector parasitic capacitance value by using a field solver with said process characterization file; and

comparing the calculated connector parasitic capacitance value with the measured parasitic capacitance to determine an effective connector width.

15. The method of claim 1, further comprising extracting parasitic capacitance by interpolating and extrapolating capacitance values in said capacitance table of said technology file.

16. The method of claim 1 further comprising outputting a parasitic extraction result in a netlist of RC values.

17. The method of claim 1 further comprising performing a simulation based on said circuit layout using said extracted parasitic capacitance.

18. The method of claim 17 further comprising optimizing said circuit layout based on said performing said simulation.

19. The method of claim 1, wherein said actual connector configuration in said IC includes vias in a first dielectric layer over and adjoining a semiconductor substrate and/or includes contacts in a second dielectric layer over and adjoining said first dielectric layer.

20. The method of claim 1 further comprising forming said actual connector configuration in a semiconductor substrate.