Transistor structure having a trench drain

• US 8,216,925 B2
• Filed: 11/01/2010
• Issued: 07/10/2012
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Davies, Robert Bruce
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US12/917,163
• Publication Number:
  US 20110045664A1
• Time in Patent Office: 617 Days
• Field of Search: 257/328, 257/341, 257/E29.03, 438/524
• US Class Current: 438/524
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Claims

1. A method to achieve planar breakdown in a drain region of a transistor, the method comprising:

forming a tub region that includes a channel region of the transistor to a first depth where the tub region is an opposite conductivity type as the drain region;

forming a trench in the drain region of the transistor to a second depth;

forming a dielectric layer overlying the trench wherein the second depth is greater than the first depth to reduce a field strength in proximity to the tub region and wherein a voltage breakdown of the transistor is increased;

forming a pedestal disposed proximate to the trench;

forming a first conductive shield disposed in the trench approximately parallel to a sidewall of the trench; and

forming a second conductive shield at least partially disposed within the pedestal.

2. The method as recited in claim 1 further comprising moving a region of maximum or nearly maximum field strength to a corner region of the trench substantially below a major surface of the transistor where the dielectric layer does not breakdown under the maximum or nearly maximum field strength.

3. The method as recited in claim 1 further comprising:

implanting dopant of a same type as the drain region in proximity to a surface of the drain region and in proximity to a channel of the transistor to support current flow out of the channel region and into the drain region; and

implanting dopant through a sidewall of the trench to support current flow in proximity to the trench adjacent to the sidewall of the trench.

4. The method as recited in claim 1 further comprising a process of etching the trench greater than two times the depth of the tub region.

5. The method as recited in claim 1 further comprising a process of providing field line edge termination for the transistor.

6. A method to fabricate a semiconductor device, comprising:

forming a tub region including a channel region of a transistor, the tub region being disposed at a first depth wherein the tub region has a conductivity type opposite to a conductivity type of a drain region of the transistor;

forming a trench formed in the drain region of the transistor to a second depth;

forming a dielectric layer overlying the trench;

wherein the second depth is greater than the first depth to reduce a field strength proximate to the tub region to increase a voltage breakdown of the transistor; and

forming a second trench at least partially disposed below the trench that is formed in the drain region of the transistor.

7. A method as claimed in claim 6, wherein a region of maximum or nearly maximum field strength is located at or near a corner region of the trench substantially below a surface of the transistor such that the dielectric layer does not breakdown under the maximum or nearly maximum field strength.

8. A method as claimed in claim 6, further comprising:

implanting a first dopant of a same type as the drain region implanted in proximity to a surface of the drain region and in proximity to the channel region of the transistor to support current flow out of the channel region and into the drain region; and

implanting a second dopant implanted through a sidewall of the trench to support current flow in proximity to the trench adjacent to the sidewall of the trench.

9. A method as claimed in claim 6, wherein the first depth of the trench is greater than two times the second depth of the tub region to result in a correspondingly increased breakdown voltage of the transistor.

10. A method as claimed in claim 6, further comprising a forming a conductive shield disposed in the trench approximately parallel to a sidewall of the trench.

11. A method as claimed in claim 6, further comprising:

forming a pedestal disposed proximate to the trench;

forming a first conductive shield disposed in the trench approximately parallel to a sidewall of the trench; and

forming a second conductive shield at least partially disposed within the pedestal.

12. A method as claimed in claim 6, wherein the second depth of the trench extends to a region away from a current carrying region of the transistor.