One-transistor pixel array

• US 8,217,433 B1
• Filed: 03/15/2012
• Issued: 07/10/2012
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US13/421,692
• Publication Number:
  US 20120168826A1
• Time in Patent Office: 117 Days
• Field of Search: 257/252, 257/253, 257/314, 257/315, 257/E29.242
• US Class Current: 257/253
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column.

Claims

1. A device comprising:

an array of chemically-sensitive field-effect transistors (chemFETs), at least some chemFETs in the array of chemFETs comprising;

a first source/drain terminal and a second source/drain terminal; and

a floating gate coupled to a passivation layer;

a plurality of first conductive lines coupled to chemFETs in the array, wherein each first conductive line in the plurality of first conductive lines is directly connected to the first source/drain terminals of chemFETs in a column in the array; and

a plurality of second conductive lines coupled to chemFETs in the array, wherein each second conductive line is directly connected to the second source/drain terminals of chemFETs in a row in the array;

bias circuitry coupled to the array to apply a read bias to selected chemFETs via the first conductive lines and second conductive lines; and

sense circuitry coupled to the array to sense charge coupled to the floating gates of selected chemFETs.

2. The device of claim 1, wherein the sensed charge indicates an ion-concentration of an analyte solution coupled to the floating gate of a selected chemFET via the passivation layer.

3. The device of claim 1, wherein:

the bias circuitry applies a read voltage to a selected first conductive line in the plurality of first conductive lines during a read interval; and

the sense circuitry includes a sample circuit to read a selected chemFET connected to the selected first conductive line and a selected second conductive line during the read interval.

4. The device of claim 3, wherein the sample circuit includes a sample and hold circuit to hold an analog value of a voltage on the selected second conductive line during the read interval, and an analog to digital converter to convert the analog value to a digital value.

5. The device of claim 3, wherein the sample circuit includes an analog to digital converter to directly convert a voltage on the selected second conductive line to a digital value during the read interval.

6. The device of claim 3, including a pre-charge circuit to pre-charge the selected second line to a pre-charge voltage level prior to the read interval.

7. The device of claim 1, wherein:

the read bias includes a read voltage on a selected first conductive line applied to boost by capacitive coupling the floating gate of a selected chemFET to a boosted voltage level, thereby inducing current flow through the selected chemFET to establish a voltage level on a selected second conductive line; and

the read bias further includes a voltage on first conductive lines connected to unselected chemFETs connected to the selected second conductive line, applied to bias by capacitive coupling the floating gates of the unselected chemFETs to an inhibit voltage level.

8. The device of claim 7, including a current sink coupled to the selected second conductive line to compensate for leakage current through unselected chemFETs connected to the selected second conductive line during the read interval.

9. A device comprising:

an array of chemically-sensitive field-effect transistors (chemFETs), at least some chemFETs in the array of chemFETs comprising;

a first source/drain terminal and a second source/drain terminal; and

a floating gate coupled to a passivation layer;

a plurality of first conductive lines coupled to chemFETs in the array, wherein each first conductive line in the plurality of first conductive lines is directly connected to the first source/drain terminals of a corresponding first plurality of chemFETs in the array; and

a plurality of second conductive lines coupled to chemFETs in the array, wherein each second conductive line in the plurality of second conductive lines is coupled to the second source/drain terminals of a corresponding second plurality of chemFETs in the array.

10. The device of claim 9, wherein each second conductive line in the plurality of second conductive lines is directly connected to the second source/drain terminals of the corresponding second plurality of chemFETs in the array.

11. The device of claim 9, wherein the chemFETs in the array are arranged in rows and columns, each first conductive line is directly connected to the first source/drain terminals of chemFETs arranged in a corresponding column in the plurality of columns, and each second conductive line is directly connected to the second source/drain terminals of chemFETs arranged in a corresponding row in the plurality of rows.

12. The device of claim 9, further comprising circuitry coupled to the plurality of first conductive lines and the plurality of second conductive lines for reading a selected chemFET directly connected to a selected first conductive line and directly connected a selected second conductive line by:

inducing current flow between the selected second conductive line and the selected first conductive line through the selected chemFET during a read interval, thereby establishing an output voltage level on the selected second conductive line;

compensating for leakage current through unselected chemFETs connected to the selected second conductive line during the read interval; and

reading the selected chemFET based on the output voltage level on the selected second conductive line.

13. The device of claim 12, wherein the circuitry for reading induces current flow between the selected second conductive line and the selected first conductive line through the selected chemFET by:

pre-charging the selected second conductive line to a pre-charge voltage level prior to the read interval;

applying a read voltage to the selected first conductive line during the read interval to boost by capacitive coupling the floating gate of the selected chemFET to a boosted voltage level, thereby inducing the current flow to establish the output voltage level on the selected second conductive line.

14. The device of claim 13, including circuitry to apply a voltage to corresponding first conductive lines connected to unselected chemFETs connected to the selected second conductive line, thereby biasing by capacitive coupling the floating gates of the unselected chemFETs to an inhibit voltage level.

15. The device of claim 14, wherein a magnitude voltage difference between the boosted voltage level and the inhibit voltage level is at least 200 mV.

16. The device of claim 13, including a switch coupled between the selected second conductive line and a reference voltage, and wherein the circuitry turns on the switch prior to the read interval to bias the selected second conductive line to the pre-charge voltage level, and turns off the switch during the read interval.

17. The device of claim 13, including a current sink coupled to the selected second conductive line to compensate for the leakage current through the remaining chemFETs during the read interval.

18. A device comprising:

an array of chemically-sensitive field-effect transistors (chemFETs) arranged in a plurality of rows and a plurality of columns, chemFETs in the array of chemFETs comprising;

a first source/drain terminal and a second source/drain terminal; and

a floating gate coupled to a passivation layer;

a plurality of column lines coupled to chemFETs in the array, wherein each column line in the plurality of column lines is directly connected to the first source/drain terminals of chemFETs arranged in a corresponding column in the plurality of columns;

a plurality of row lines coupled to chemFETs in the array, wherein each row line in the plurality of row lines is directly connected to the second source/drain terminals of chemFETs arranged in a corresponding row in the plurality of rows;

circuitry coupled to the plurality of column lines and row lines for reading a selected chemFET connected to a selected column line and a selected row line, the circuitry comprising;

bias circuitry coupled to the row lines to apply a read voltage to the selected row line in the plurality of row lines during a read interval, and to apply voltages to corresponding row lines and corresponding column lines connected to unselected chemFETs connected to the selected column line; and

sense circuitry to sense an ion-concentration of an analyte solution coupled to the floating gate via the passivation layer in the selected chemFET based on a sampled voltage level on the selected column line, wherein the sampled voltage level is established based on the current flowing on the selected column line.

19. The device of claim 18, wherein the sense circuitry includes a current sink coupled to the selected column line to compensate for leakage current through the remaining chemFETs connected to the selected column line.

20. The device of claim 18, wherein the sense circuitry includes:

a pre-charge circuit to pre-charge a selected column line to a pre-charge voltage level prior to a read interval; and

a sample circuit to read the selected chemFET based on the sampled voltage level on the selected column line during the read interval.