Hermetic MEMS device and method for fabricating hermetic MEMS device and package structure of MEMS device

• US 8,217,474 B2
• Filed: 12/28/2009
• Issued: 07/10/2012
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Solid State System Co., Ltd.
• Original Assignee: Solid State System Co., Ltd.
• Inventors: Lee, Chien-Hsing, Hsieh, Tsung-Min, Liou, Jhyy-Cheng
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): KARIMY, MOHAMMAD TIMOR
• Application Number:
  US12/647,559
• Publication Number:
  US 20110156106A1
• Time in Patent Office: 925 Days
• Field of Search: 257/414, 257/254, 257/E27.062, 257/E23.001, 257/E29.234
• US Class Current: 257/414
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 2207/092 Buried interconnects in the substrate or in the lid
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A hermetic microelectromechanical system (MEMS) package includes a CMOS MEMS chip and a second substrate. The CMOS MEMS Chip has a first substrate, a structural dielectric layer, a CMOS circuit and a MEMS structure. The structural dielectric layer is disposed on a first side of the first structural substrate. The structural dielectric layer has an interconnect structure for electrical interconnection and also has a protection structure layer. The first structural substrate has at least a hole. The hole is under the protection structure layer to form at least a chamber. The chamber is exposed to the environment in the second side of the first structural substrate. The chamber also comprises a MEMS structure. The second substrate is adhered to a second side of the first substrate over the chamber to form a hermetic space and the MEMS structure is within the space.

Claims

1. A hermetic microelectromechanical system (MEMS) package, comprising:

a CMOS MEMS chip, having a silicon substrate and a structural dielectric layer, wherein the silicon substrate have a first surface and a second surface opposite to the first surface and has a MEMS region and a CMOS integrated-circuit (IC) region, wherein CMOS transistors are formed on the first surface of the silicon substrate in the CMOS IC region and the silicon substrate is used as a transistor substrate of the CMOS transistors, wherein the silicon substrate is structural to form a chamber at the MEMS region and a MEMS structure within the chamber, wherein the structural dielectric layer comprises an interconnection structure formed on the first surface of the silicon substrate over the CMOS IC region and the MEMS region, wherein the interconnection structure is used to connect the CMOS transistors to form a CMOS IC and electrically couple between the CMOS IC and the MEMS structure within the chamber, wherein the interconnection structure further comprises a protection structure layer formed in the structural dielectric layer and the chamber is covered by the protection structure layer,

wherein the chamber is exposed to an environment at the second surface of the silicon substrate, the interconnection structure further comprises an output pad structure to couple an electrical signal of the CMOS MEMS chip out; and

a first substrate, adhered to the second surface of the first substrate on the chamber via an adhesive layer to form a hermetic space, wherein the MEMS structure is within the hermetic space.

2. The hermetic MEMS package of claim 1, wherein the MEMS structure comprises a portion of the silicon substrate.

3. The hermetic MEMS package of claim 1, wherein the MEMS structure comprises a portion of the structural dielectric layer.

4. The hermetic MEMS package of claim 3, wherein the MEMS structure comprises a dielectric layer and a metal layer enclosing the dielectric layer.

5. The hermetic MEMS package of claim 1, wherein the protection structure layer comprises a hard mask layer or a structural conductive layer.

6. The hermetic MEMS package of claim 5, wherein the structural conductive layer comprises a grid structure over the chamber and a shielding layer over the MEMS structure and a CMOS circuit of the CMOS MEMS chip.

7. The hermetic MEMS package of claim 1, further comprising a metal bump on the output pad structure to couple the electrical signal out.

8. The hermetic MEMS package of claim 1, further comprising a second substrate disposed on the structural dielectric layer by an adhesive layer, wherein the second substrate also includes an extending output pad structure in electric connection with the output pad structure of the CMOS MEMS chip.

9. The hermetic MEMS package of claim 8, wherein the extending output pad structure in the second substrate layer electrically connected with the output pad structure of CMOS MEMS chip comprises conductive bumps or an adhesive layer on the output pad structure.

10. The hermetic MEMS package of claim 9, wherein the conductive bumps include stud bumps or solder bumps, wherein the adhesive layer on the output pad structure includes solder paste or conductive or non-conductive epoxy.

11. The hermetic MEMS package of claim 1, wherein the first substrate is a flat layer without circuit.

12. The hermetic MEMS package of claim 1, wherein the first substrate adhered to the second side of the first substrate comprises an adhesive layer or a fusion layer.

13. A package structure of microelectromechanical system (MEMS) device, comprising:

a CMOS MEMS die, comprising;

a CMOS MEMS chip, having a silicon substrate and a structural dielectric layer, wherein the silicon substrate have a first surface and a second surface opposite to the first surface and has a MEMS region and a CMOS integrated-circuit (IC) region, wherein CMOS transistors are formed on the first surface of the silicon substrate in the CMOS IC region and the silicon substrate is used as a transistor substrate of the CMOS transistors, wherein the silicon substrate is structural to form a chamber at the MEMS region and a MEMS structure within the chamber, wherein the structural dielectric layer comprises an interconnection structure formed on the first surface of the silicon substrate over the CMOS IC region and the MEMS region, wherein the interconnection structure is used to connect the CMOS transistors to form a CMOS IC and electrically couple between the CMOS IC and the MEMS structure within the chamber, wherein the interconnection structure further comprises a protection structure layer formed in the structural dielectric layer and the chamber is covered by the protection structure layer, wherein the chamber is exposed to an environment at the second surface of the silicon substrate, the interconnection structure further comprises an output pad structure to couple an electrical signal of the CMOS MEMS chip out; and

a first substrate, adhered to the second surface of the silicon substrate via an adhesive layer over the chamber to form a hermetic space, wherein the MEMS structure is within the hermetic space;

a packaging circuit substrate, for holding the MEMS die; and

a molding layer, encapsulating over the MEMS die and the packaging circuit substrate.

14. The package structure of MEMS device of claim 13, wherein the packaging circuit substrate has a lead frame, having a die pad for holding the MEMS die and a plurality of leads being connected with the CMOS circuit in the CMOS MEMS chip via bonding wires.

15. The package structure of MEMS device of claim 13, wherein the MEMS die further comprises a protection layer over the MEMS structure, and the protection layer has an opening to expose the output pad structure.

16. The package structure of MEMS device of claim 13, wherein the MEMS die further comprises a protection cap layer over the MEMS structure with an indent space, and the protection cap layer has an opening to expose the output pad structure.

17. The package structure of MEMS device of claim 13, wherein the packaging circuit substrate is a printed circuit board, and the MEMS die is electrically connected to the printed circuit board by bonding wire.

18. The package structure of MEMS device of claim 13, wherein the packaging circuit substrate is a printed circuit board, and the MEMS die is electrically connected to the printed circuit board by solder bump in flip-chip packaging structure.

19. The package structure of MEMS device of claim 13, wherein the MEMS structure comprises a portion of the silicon substrate.

20. The package structure of MEMS device of claim 13, wherein the MEMS structure comprises a portion of the structural dielectric layer.

21. The package structure of MEMS device of claim 20, wherein the MEMS structure comprises a dielectric layer and a metal layer enclosing the dielectric layer.

22. The package structure of MEMS device of claim 13, wherein the protection structure layer comprises a hard mask layer or a structural conductive layer.

23. The package structure of MEMS device of claim 22, wherein the structural conductive layer comprises a grid structure over the chamber and a shielding layer over the MEMS structure and the CMOS circuit.

24. The package structure of MEMS device of claim 13, wherein a first substrate adhered to a second side of the first substrate comprise an adhesive layer or a fusion layer.