Method of operating inverter

• US 8,217,680 B2
• Filed: 03/29/2011
• Issued: 07/10/2012
• Est. Priority Date: 10/01/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sangwook, Song, Ihun, Kim, Changjung, Park, Jaechul, Kim, Sunil
• Primary Examiner(s): LE, DON P
• Application Number:
  US13/064,492
• Publication Number:
  US 20110175647A1
• Time in Patent Office: 469 Days
• Field of Search: 326/21, 326/26, 326/27, 326/82, 326/83, 326/101, 326/102, 326/103
• US Class Current: 326/83
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method of operating inverter may include providing a load transistor and a driving transistor connected to the load transistor wherein at least one of the load transistor and the driving transistor has a double gate structure, and varying a threshold voltage of the at least one of the load transistor and the driving transistor having the double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter.

Claims

1. A method of operating an inverter comprising:

providing a load transistor and a driving transistor connected to the load transistor, wherein at least one of the load transistor and the driving transistor has a double gate structure; and

varying a threshold voltage of only the at least one of the load transistor and the driving transistor having the double gate structure.

2. The method of claim 1, wherein varying the threshold voltage includes supplying a voltage to at least one of two gates of the transistor having the double gate structure.

3. The method of claim 2, wherein the driving transistor has the double gate structure, and varying the threshold voltage includes supplying a negative (−

) voltage to one of two gates of the driving transistor.

4. The method of claim 2, wherein the driving transistor has the double gate structure, and varying the threshold voltage includes supplying a positive (+) voltage to two gates of the driving transistor.

5. The method of claim 2, wherein the load transistor has the double gate structure, and varying the threshold voltage includes supplying a positive (+) voltage to one of two gates of the load transistor.

6. The method of claim 1, further comprising:

supplying a normal operational voltage to the inverter after adjusting the threshold voltage.

7. The method of claim 1, wherein one of the load transistor and the driving transistor has the double gate structure, and the other of the load transistor and the driving transistor has a single gate structure.

8. The method of claim 1, wherein the load transistor and the driving transistor have the double gate structure.

9. The method of claim 1, wherein the load transistor and the driving transistor are oxide thin film transistors (TFTs).

10. The method of claim 9, wherein the load transistor and the driving transistor include channel layers made of a ZnO-based oxide.