Reference signal generator circuit for an analog-to-digital converter of a microelectromechanical acoustic transducer, and corresponding method

• US 8,217,821 B2
• Filed: 06/22/2010
• Issued: 07/10/2012
• Est. Priority Date: 06/23/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Padovani, Igino, David, Filippo
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US12/821,022
• Publication Number:
  US 20100321103A1
• Time in Patent Office: 749 Days
• Field of Search: 341/118, 341/120, 341/143, 341/155, 323/268, 323/182, 323/313, 323/277, 327/271, 327/282, 327/285, 327/286, 327312-317, 327/538, 327/539
• US Class Current: 341/155
• CPC Class Codes: G05F 3/08 wherein the variable is dc

Abstract

A reference signal generator circuit for an analog-to-digital converter, the circuit having a signal-generation stage to generate a first reference signal on a first reference terminal, and a filtering circuit arranged between the generator stage and the analog-to-digital converter to determine a filtering of disturbance present on the first reference signal and supply at output on a second reference terminal a second filtered reference signal, the filtering circuit having a switching circuit to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once the startup step is terminated.

Claims

1. A reference signal generator circuit, comprising:

a first reference terminal and a second reference terminal, the first reference terminal structured to receive a first reference signal;

a filtering circuit arranged between the first reference terminal and the second reference terminal, the filtering circuit structured to filter a disturbance on the first reference signal and to supply at output on the second reference terminal a filtered reference signal, the filtering circuit including a first diode element and a first switch circuit each coupled between the first and second reference terminals;

a control circuit structured to actuate the first switch circuit in a first operative condition of low-impedance conduction in which the first switch circuit constitutes a low-impedance coupling between the first reference terminal to the second reference terminal during startup of the reference signal generator circuit and in a second operative condition of high impedance in which the first switch circuit acts as a second diode element in antiparallel with the first diode element and provides a high-impedance connection between the first reference terminal and the second reference terminal once startup is terminated.

2. The circuit of claim 1, wherein the first switch circuit includes a first transistor in diode configuration and the first diode element is a second transistor in diode configuration.

3. The circuit of claim 2, wherein the control stage includes a third transistor and a fourth transistor coupled in inverter configuration, the third and fourth transistors structured to be alternatively controlled in conduction and inhibition by a first control signal and structured to bias alternatively a control terminal of the first transistor with a ground signal or with the first reference signal to provide alternatively the low-impedance conduction or the high-impedance conduction between the first reference terminal and the second reference terminal.

4. The circuit of claim 2, further comprising a control loop structured to drive the first transistor in low-impedance conduction when the filtered reference signal presents a given relation with a threshold.

5. The circuit of claim 4, wherein the control loop includes a comparator device and a logic block, the comparator device having a first input terminal, a second input terminal, and an output terminal, the comparator device structured to receive on the first input terminal the filtered reference signal and on the second input terminal a comparison signal correlated to the first reference signal to define the threshold and to supply on the output terminal a result of a comparison between the comparison signal and the filtered reference signal, and the logic block having a first input terminal, a second input terminal, and an output terminal, the logic block structured to receive on the first input terminal the result of the comparison and on the second input terminal the first control signal, and to supply on the output terminal a second control signal that is adapted to drive the first transistor in low-impedance conduction when the filtered reference signal drops below the threshold.

6. The circuit of claim 1, wherein the circuit includes a filter capacitor coupled to the second reference terminal, and wherein the first switch element and the filter capacitor are structured to form a lowpass filter when the first switch element is in high impedance conduction.

7. A reference signal generator circuit, comprising:

a first reference terminal and a second reference terminal;

a signal-generation stage coupled to the first reference terminal;

a filtering circuit coupled between the first reference terminal and the second reference terminal;

a switch circuit coupled to the first and second reference terminals and in parallel with the filtering circuit; and

a buffer circuit coupled to the second reference terminal and configured to be coupled to the capacitive load, the buffer circuit configured to drive the capacitive load;

the buffer circuit including;

a single-stage amplifier in voltage-follower configuration and having a non-inverting input coupled to the filtering circuit, and

a compensation capacitor coupled to an output terminal of the single-stage amplifier and configured to be coupled in parallel to the capacitive load.

8. The circuit of claim 7, wherein the filtering circuit includes a first high-impedance resistive element arranged between the first reference terminal and the second reference terminal, and wherein the switch circuit includes a first switch element connected in parallel to the first resistive element and structured to be actuated to short-circuit the first resistive element.

9. The circuit of claim 8, wherein the first resistive element includes a first diode element, and wherein the first switch element includes a first transistor, the reference signal generator circuit including a control stage structured to actuate the first transistor in a first operative condition of low-impedance conduction in which it provides a low-impedance connection between the first reference terminal and the second reference terminal to short-circuit the first diode element, and in a second operative condition of high impedance in which it provides a high-impedance connection between the first reference terminal and the second reference terminal.

10. The circuit of claim 9, wherein the first diode element is a second transistor in diode configuration connected between the first reference terminal and the second reference terminal.

11. The circuit of claim 10, wherein the control stage includes a third transistor and a fourth transistor that are coupled together to form an inverter, the third and fourth transistors alternatively controlled in conduction and inhibition by a first control signal and structured to bias alternatively a control terminal of the first transistor with a ground signal or with the first reference signal to provide alternatively the low-impedance connection or the high-impedance connection between the first reference terminal and the second reference terminal.

12. The circuit of claim 10, wherein the filtering circuit includes a filter capacitor connected to the second reference terminal, and the first transistor and the filter capacitor are coupled together to form a low pass filter when the first transistor is in the second operative condition of high-impedance.

13. An electronic device, comprising:

an analog-to-digital converter having an input terminal and an input stage that includes a capacitive load;

a reference signal generator circuit structured to supply a filtered reference signal to the input terminal of the analog-to-digital converter, the reference signal generator circuit including;

a first reference terminal and a second reference terminal;

a signal-generation stage structured to generate a first reference signal on the first reference terminal;

a filtering circuit coupled between the first reference terminal and the second reference terminal and further coupled to the analog-to-digital converter, the filtering circuit configured to filter a disturbance on the first reference signal and to supply at output on the second reference terminal a filtered reference signal; and

a switch circuit coupled to the first reference terminal and to the second reference terminal; and

a buffer circuit having an output terminal coupled to the analog-to-digital converter and structured to drive the capacitive load, the buffer circuit including a single-stage amplifier in voltage-follower configuration and having a non-inverting input structured to receive the filtered reference signal, and a compensation capacitor coupled to the output terminal of the buffer circuit and further coupled in parallel to the capacitive load.

14. The device of claim 13, including an acoustic transducer configured to generate an analog detection signal, and wherein the analog-to- digital converter is operatively coupled to the acoustic transducer and structured to convert the analog detection signal into a digital detection signal.

15. The device of claim 14, wherein the acoustic transducer is a MEMS microphone of a capacitive type, and the reference signal generator circuit is of a type integrated in CMOS technology.

16. The device of claim 13, wherein the electronic device is chosen from the group that includes:

a cellphone, a PDA, a notebook, a voice recorder, an audio reader with voice-recorder function, a console for videogames, a hydrophone, a hearing-aid device.

17. A circuit, comprising:

first and second nodes;

a signal generator structured to generate a first reference signal at the first node;

a filter circuit coupled to the first node and structured to receive the first reference signal and to generate a filtered reference signal at the second node;

a first transistor coupled between the first and second nodes and structured to be actuated in a first operative condition of low-impedance conduction between the first and second nodes and in a second operative condition of high impedance conduction between the first and second nodes, the first transistor including a control terminal;

a second transistor in diode configuration coupled between the first and second nodes, the second transistor including a control terminal; and

a switch circuit coupled to the first and second nodes and structured to selectively connect the signal generator directly to the second node to bypass the filter circuit, and to connect the filter circuit to the first and second nodes, the switch circuit including;

a control circuit coupled to the first transistor and structured to bias alternatingly the control terminal of the first transistor with a ground signal or the first reference signal to provide alternatingly the low-impedance conduction or the high-impedance conduction between the first and second nodes;

a comparator having a first input terminal configured to receive the filtered reference signal and a second input terminal configured to receive a comparison signal correlated to the first reference signal to define a threshold, and an output terminal, the comparator configured to supply on the output terminal a result of a comparison between the comparison signal and the filtered reference signal; and

a logic block having a first input terminal, a second input terminal, and an output terminal, the logic block structured to receive a first control signal on the first input terminal, to receive the result from the comparator on the second input terminal, and to supply on the output terminal a second control signal to drive the first transistor in low-impedance conduction when the filtered reference signal drops below the threshold.

18. The circuit of claim 17, the circuit further including a buffer circuit coupled to the second node, the buffer circuit having a single-stage amplifier in voltage-follower configuration and structured to receive the filtered reference signal and to drive a capacitive load.