Methods of calibrating a clock using multiple clock periods with a single counter and related devices and methods

• US 8,219,345 B2
• Filed: 12/17/2010
• Issued: 07/10/2012
• Est. Priority Date: 05/27/2008
• Status: Expired due to Fees

• Current Assignee: Sony Ericsson Mobile Communications AB (Sony Group Corp.)
• Original Assignee: Sony Ericsson Mobile Communications AB (Sony Group Corp.)
• Inventors: Haartsen, Jacobus Cornelis, Stek, Aalbert
• Primary Examiner(s): Bhat, Aditya
• Application Number:
  US12/971,272
• Publication Number:
  US 20110087449A1
• Time in Patent Office: 571 Days
• Field of Search: 368 46- 47, 327/99, 702/89
• US Class Current: 702/89
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods may include generating incremented counter values at a counter responsive to edges of the second clock signal. For at least two of the plurality of calibration periods, an initial incremented counter value from the counter may be stored in memory at an initial edge of the first clock signal for the respective calibration period, a final incremented counter value may be stored in memory at a final edge of the clock signal for the respective calibration period, and the at least two of the plurality of calibration periods may be overlapping with different initial and final edges of the first clock signal. For each of the plurality of calibration periods, a number of edges of the second clock signal occurring during the respective calibration period may be determined using the initial and final incremented counter values stored in memory. A relationship between the first and second clock signals may be determined using a sum of a number of edges of the second clock signal occurring during each of the plurality of calibration periods and using a sum of a number of first clock signal cycles occurring during each of the plurality of calibration periods.

Claims

1. A method of calibrating a first clock signal, the method comprising:

generating incremented counter values, using a counter, a calibration circuit, and/or a processor, responsive to edges of a second clock signal generated by a second clock coupled to a receiver;

for at least two different edges of the first clock signal, performing calculations based on respective incremented counter values using the calibration circuit and/or the processor;

determining a relationship between the first and second clock signals using linear regression using the calculations based on the respective incremented counter values for the at least two different edges of the first clock signal, wherein determining comprises determining the relationship using the calibration circuit and/or the processor;

during a first waking period, operating the receiver using the second clock;

during a sleep period after the first waking period, timing a duration of the sleep period using the first clock with the second clock turned off; and

during a second waking period after the sleep period, operating the receiver using the second clock.

2. A method according to claim 1 wherein performing calculations based on the respective incremented counter values comprises performing the calculations based on the respective incremented counter values taken at edges of the same transition type of respective cycles of the first clock signal.

3. A method according to claim 2 wherein determining the relationship between the first and second clock signals using linear regression comprises calculating a regression coefficient using the incremented counter values from the at least two different edges of the first clock signal.

4. A method according to claim 1 wherein performing calculations based on the respective incremented counter values comprises integrating incremented counter values taken at edges of the same transition type of different cycles of the first clock signal.

5. A method according to claim 1 wherein generating incremented counter values comprises generating incremented counter values at the counter responsive to edges of the second clock signal of the same transition type.

6. A method of calibrating a first clock signal, the method comprising:

generating incremented counter values, using a counter, a calibration circuit, and/or a processor, responsive to edges of a second clock signal;

for at least two different edges of the first clock signal, performing calculations based on respective incremented counter values using the calibration circuit and/or the processor; and

determining a relationship between the first and second clock signals using linear regression using the calculations based on the respective incremented counter values for the at least two different edges of the first clock signal, wherein determining comprises determining a relationship using the calibration circuit and/or the processor,

wherein at a first edge of the first clock signal the counter and first and second adders are set to initial values,

wherein at a second edge of the first clock signal after the first edge, an incremented counter value generated by the counter is added to the initial value of the first adder to generate a second value of the first adder, and the initial value of the first adder is added to the initial value of the second adder to generate a second value of the second adder, and

wherein at a third edge of the first clock signal after the second edge, an incremented counter value generated by the counter is added to the second value of the first adder to generate a third value of the first adder, and the second value of the first adder is added to the first value of the second adder to generate a third value of the second adder.

7. A method according to claim 6 wherein the second clock is coupled to a receiver, the method further comprising:

during a first waking period, operating the receiver using the second clock;

during a sleep period after the first waking period, timing a duration of the sleep period using the first clock with the second clock turned off; and

during a second waking period after the sleep period, operating the receiver using the second clock.

8. A method according to claim 6 wherein performing calculations based on the respective incremented counter values comprises performing the calculations based on the respective incremented counter values taken at edges of the same transition type of respective cycles of the first clock signal.

9. A method according to claim 8 wherein determining the relationship between the first and second clock signals using linear regression comprises calculating a regression coefficient using the incremented counter values from the at least two different edges of the first clock signal.

10. A method according to claim 6 wherein performing calculations based on the respective incremented counter values comprises integrating incremented counter values taken at edges of the same transition type of different cycles of the first clock signal.

11. A method according to claim 6 wherein generating incremented counter values comprises generating incremented counter values at the counter responsive to edges of the second clock signal of the same transition type.