System and apparatus for enhancing data storage efficiency of a flash memory by reducing time for reorganizing data

• US 8,219,764 B2
• Filed: 03/23/2011
• Issued: 07/10/2012
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: Silicon Motion
• Original Assignee: Silicon Motion
• Inventors: Lee, Chun-Kun, Hsiao, Wei-Yi
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US13/069,937
• Publication Number:
  US 20110173381A1
• Time in Patent Office: 475 Days
• Field of Search: 711/103, 711/156
• US Class Current: 711/156
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Claims

1. An apparatus for managing flash memory data, comprising:

a flash memory including a flash memory buffer, a destination block, and

a temporary block; and

a controller, external to the flash memory, comprising an external buffer;

wherein the controller is configured to receive a write command and data having a destination address corresponding to the destination block, store the data in the external buffer, and, responsive to the write command, write the data in the external buffer to the flash memory buffer; and

wherein the controller is further configured to determine if the flash memory buffer is full and, if the flash memory buffer is not full, the controller is configured to cause the data to be written to the temporary block.

2. The apparatus of claim 1, wherein the controller is configured to receive the write command and the data having a destination address from a host external to the apparatus.

3. The apparatus of claim 1, wherein the controller is further configured to assign a temporary address to the data within the flash memory buffer and, responsive thereto, the data is written to the temporary block.

4. The apparatus of claim 1, wherein when the flash memory buffer is full, the controller is configured to cause the data to be written to the destination block in accordance with the destination address.

5. The apparatus of claim 2, wherein the controller is configured to determine whether storage of data from the host in the external buffer has stopped and the controller is further configured to determine if the flash memory buffer is full responsive to the determination that storage of data from the host to the external buffer has stopped.

6. The apparatus of claim 2, wherein the controller is configured to determine whether storage of data from the host in the external buffer has stopped, determine whether the flash memory buffer is full, and cause the data to be written to the temporary block if the flash memory buffer is not full and the storage of data from the host in the external buffer has stopped.

7. The apparatus of claim 6, wherein when the data are still being stored in the external buffer and the flash memory buffer is full, the controller is configured to cause the data to be written into the destination block within the flash memory according to the destination address, and when the data are completely written to the destination block, the flash memory is configured to execute a write command.

8. An apparatus for managing flash memory data, comprising:

a flash memory including a flash memory buffer, a destination block, and a temporary block; and

a controller, external to the flash memory, comprising an external buffer;

wherein the controller is configured to receive a write command and data having a destination address corresponding to the destination block, to store the data in the external buffer, and, responsive to the write command, to write the data in the external buffer to the flash memory buffer; and

wherein the controller is further configured to determine if the flash memory buffer is full and, if the flash memory buffer is not full, the controller, responsive to the write command, is configured to re-assign a temporary address to the data, to write the data, having the re-assigned temporary address, in the external buffer to the flash memory buffer, and to write the data into the temporary block of the flash memory in accordance with the temporary address.

9. The apparatus of claim 8, wherein when the flash memory buffer is full, the controller is configured to cause the data to be written to the destination block in accordance with the destination address.

10. The apparatus of claim 8, wherein the controller is configured to receive the write command and the data having a destination address from a host external to the apparatus.

11. The apparatus of claim 10, wherein the controller is further configured to wait for the host to transmit the data to the external buffer, to determine whether the data are first transmitted to the external buffer and, if the data are first transmitted to the external buffer, to write the data in the external buffer to the flash memory buffer.

12. The apparatus of claim 10, wherein the controller is configured to determine if the flash memory buffer is full, responsive to a determination by the controller that the host has completed transmitting data to the external buffer.

13. The apparatus of claim 11, wherein the controller is configured to determine whether the transmission of data from the host to the external buffer has stopped to determine whether the flash memory buffer is full, and to cause the data to be written to the temporary block if the flash memory buffer is not full and the storage of data from the host in the external buffer has stopped.

14. The apparatus of claim 13, wherein the controller is further configured to cause the writing of the data to the destination block within the flash memory according to the destination address when the data are still being written to the external buffer and the flash memory buffer is full, and to cause execution of the writing command when the data are completely written into the destination block and to then cause the writing of the data in the external buffer to the flash memory buffer.

15. A system for managing flash memory data, comprising:

a flash memory including a flash memory buffer, a destination block, and a temporary block;

a controller including a buffer external to the flash memory; and

a host;

wherein the controller is configured to receive, from the host, a write command and data having a destination address corresponding to the destination block, to store the data in the external buffer, and, responsive to the write command, write the data in the external buffer to the flash memory buffer; and

wherein the controller is further configured to determine if the flash memory buffer is full and, if the flash memory buffer is not full, to cause the data to be written to the temporary block.

16. The system of claim 15, wherein, when the flash memory buffer is full, the controller is configured to cause the data to be written in the destination block within the flash memory in accordance with the destination address.

17. The system of claim 15, wherein prior to writing the data in the external buffer to the flash memory buffer, the controller is configured to wait for the host to transmit the data to the external buffer, and to write the data in the external buffer to the flash memory buffer when the data are not first transmitted to the external buffer.

18. The system of claim 17, wherein prior to determining if the flash memory buffer is full, the controller is further configured to determine whether the host has completed writing data to the external buffer and, if the writing has been completed, determining if the flash memory buffer is full.

19. The system of claim 17, wherein prior to determining if the flash memory buffer is full, the controller is further configured to determine whether the host has completed writing data to the external buffer and, when the data are still being written to the external buffer, the controller is configured to determine whether the flash memory buffer is full and, responsive to the determination that the flash memory buffer is not full, to wait for the host to transmit the data to the external buffer, and to write the data in the external buffer to the flash memory buffer when the data are not first transmitted to the external buffer.

20. The system of claim 19, wherein when the data are still being written to the external buffer and the flash memory buffer is full, the data are written into the destination block within the flash memory in accordance with the destination address and, when the data are completely written to the destination block, the flash memory executes a write command prior to waiting for the host to transmit the data to the external buffer and writing the data in the external buffer to the flash memory buffer when the data are not first transmitted to the external buffer.