Virtual memory interface

• US 8,219,778 B2
• Filed: 02/27/2008
• Issued: 07/10/2012
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Palladino, Michael, Gyllenhammer, Carl, Kleveland, Bendik
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): Verderamo, III, Ralph A
• Application Number:
  US12/037,940
• Publication Number:
  US 20090216964A1
• Time in Patent Office: 1,595 Days
• Field of Search: None
• US Class Current: 711/203
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.

Claims

1. Apparatus, comprising:

a memory comprising data storage locations addressable by physical addresses; and

a virtual memory interface comprising a direct memory access (DMA) controller operable to interface to the memory and operable to receive a virtual address from a bus and to internally translate the virtual address into a physical address, wherein the virtual address is an address in a flat memory linear addressing space and the virtual address is applied as an index into a sequence of the physical addresses that is ordered in accordance with a group of buffers, wherein each buffer is defined by an address pointer which points to a physical reference address and a buffer length, wherein the DMA controller comprises;

an index register configured to store the virtual address;

a descriptor register configured to store a list pointer pointing to a buffer list associated with the virtual address;

a state machine for controlling operations of the DMA controller and configured to directly determine the physical address,

wherein under control of said state machine upon receipt of a data transfer request, the state machine stores an associated virtual address in the index register and stores an associated buffer list pointer in the descriptor register and determines one of a plurality of buffers from said buffer list according to the virtual address of the data transfer request by using said list pointer, wherein said state machine loads a physical reference address and buffer length through the selected buffer, determines the physical address by determining an offset within the selected buffer using said index register, and performs said data transfer request using said physical address.

2. The apparatus of claim 1, wherein in response to receipt of the virtual address, the DMA controller maps the virtual address to a target one of the physical addresses having a sequence position offset from the physical reference address in the sequence by an amount corresponding to an amount by which the virtual address is offset from a reference position in the flat memory linear addressing space.

3. The apparatus of claim 2, wherein in mapping the virtual address to the respective physical address, the DMA controller increments a buffer address list index to an index value of a target one of the buffers encompassing the target physical address and incrementing a buffer offset by an amount corresponding to an offset between a starting physical address of the target buffer and the target physical address.

4. The apparatus of claim 1, wherein in response to receipt of the virtual address in association with a data transfer request, the DMA controller uses the virtual address to identify a target one of the physical addresses in a target one of the buffers and performs data transfer operations with respect to the target storage location at the identified physical address.

5. The apparatus of claim 1, wherein the group of buffers is stored in said memory and accessed through the descriptor register in said DMA controller.

6. The apparatus of claim 5, wherein the DMA controller is operable to build a list of buffer reference elements after data is written to the buffers.

7. The apparatus of claim 5, wherein in response to a request to write data to the memory, the DMA controller builds the list of buffer reference elements in accordance with a group of buffers scattered in the memory.

8. The apparatus of claim 5, wherein the DMA controller comprises an index register storing a virtual address and a window register storing an offset to said virtual address.

9. The apparatus of claim 8, wherein the DMA controller comprises a plurality of counter registers used for mapping the virtual address to said physical address.

10. The apparatus of claim 1, further comprising a wireless transceiver operable to transmit and receive packets of data, wherein the received packet data is stored in buffers scattered in the memory and each of the received packets is associated with a respective list of buffer reference elements each of which comprises (i) a respective buffer pointer to a respective buffer containing data of the packet and (ii) a size of the respective buffer;

wherein, for each of the received packets, the DMA controller is operable to apply a virtual address in a respective flat memory linear addressing space as an index into a sequence of the physical addresses that is ordered in accordance with the respective buffer reference element list.

11. The apparatus of claim 10, wherein the memory, the DMA controller, and the wireless transceiver are implemented on a single semiconductor chip.

12. An integrated wireless transceiver device, comprising:

a memory comprising data storage locations addressable by physical addresses;

a wireless transceiver operable to transmit and receive packets of data;

logic operable to store packet data in buffers scattered in the memory and to associate with each of the stored packets a respective list of buffer reference elements each of which comprises (i) a respective buffer pointer to a respective buffer containing data of the packet and (ii) a size of the respective buffer; and

a virtual memory interface comprising a direct memory access (DMA) controller operable to interface to the memory and operable to receive a virtual address from a bus and to internally translate the virtual address into a physical address, wherein the virtual address is an address in a flat memory linear addressing space and the virtual address is applied as an index into a sequence of the physical addresses that is ordered in accordance with a group of said buffers, wherein the DMA controller comprises;

an index register configured to store the virtual address;

a descriptor register configured to store a list pointer pointing to a buffer list associated with the virtual address;

a state machine for controlling operations of the DMA controller and configured to directly determine the physical address,

wherein under control of said state machine upon receipt of a data transfer request, the state machine stores an associated virtual address in the index register and stores an associated list pointer in the descriptor register and selects one of a plurality of buffers from said buffer list according to the virtual address of the data transfer request by using said list pointer, wherein said state machine loads a physical reference address and buffer length through the selected buffer, determines the physical address by determining an offset within the selected buffer using said index register, and performs said data transfer request using said physical address.

13. The apparatus of claim 12, wherein

in response to receipt of a respective one of the virtual addresses in association with a data transfer request with respect to a particular packet, the virtual memory interface is operable to resolve the received virtual address to a target one of the physical addresses based on the respective indexing and to perform data transfer operations with respect to the data storage location at the target physical address.

14. The apparatus of claim 12, wherein the virtual memory interface is operable to provide a bus master device with random access to individual ones of the data storage locations.

15. The apparatus of claim 12, wherein the memory, the wireless transceiver, the logic, and the virtual memory interface are implemented on a single semiconductor chip.

16. A method, comprising:

fetching a list of buffer reference elements each of which comprises (i) a respective buffer pointer corresponding to a respective one of physical addresses of data storage locations in a memory and (ii) a respective buffer size;

ordering ones of the physical addresses into a continuous sequence of virtual addresses in accordance with the list of buffer reference elements;

receiving a virtual address by a direct memory access (DMA) controller and determining an associated physical address within said DMA controller according to the ordered physical addresses wherein under control of a state machine within said DMA controller the virtual address is stored in an index register and an associated list pointer is stored in a descriptor register, wherein said state machine loads a physical reference address and buffer length through said list pointer and determines a physical address using said index register, said loaded physical reference address; and

performing data transfer operations with respect to the target data storage locations from or to said memory by means of said DMA controller using said physical address.

17. The method of claim 16, further comprising

in response to receipt of the virtual address, selecting as a target physical address a physical address having a sequence position offset from a reference position in the sequence by an amount corresponding to an amount by which the virtual address is offset from a reference position in the flat memory linear addressing space.

18. The method of claim 17, wherein the selecting comprises

incrementing a buffer address list index to an index value of the buffer reference element that comprises a buffer pointer to a target buffer encompassing the target physical address, and

incrementing a buffer offset by an amount corresponding to an offset between the physical address of the target buffer and the target physical address.

19. The method of claim 16, wherein the accessing comprises

in response to receipt of the virtual address in association with a data transfer request, using the virtual address to identify a target one of the physical addresses in a target buffer scattered in the memory and performing data transfer operations with respect to the data storage location at the target physical address.

20. The method of claim 16, further comprising building the list of buffer reference elements in accordance with a group of buffers scattered in the memory.

21. A method, comprising:

wirelessly transmitting and receiving packets of data;

storing packet data in buffers scattered in a memory that comprises data storage locations addressable by physical addresses;

associating with each of the stored packets a respective list of buffer reference elements each of which comprises (i) a respective buffer pointer to a respective buffer containing data of the packet and (ii) a size of the respective buffer; and

providing access to individual ones of the data storage locations by means of a direct memory access (DMA) controller based on respective orderings of ones of the physical addresses into respective sequences in accordance with respective ones of the lists of buffer reference elements and on a respective indexing of each the ordered physical address sequences with consecutive virtual addresses in a flat memory linear addressing space, wherein for performing an access to the data storage locations using a virtual address, the DMA controller under control of a state machine within said DMA controller determines the physical address of a virtual address within the DMA controller by storing the virtual address in an index register and an associated list pointer in a descriptor register, wherein said state machine loads a physical reference address and buffer length through a selected buffer reference element and determines a physical address by determining an offset within the selected buffer using said index register, and performs said access using said physical address.

22. The method of claim 21, wherein in response to receipt of a respective one of the virtual addresses in association with a data transfer request with respect to a particular packet,

resolving the received virtual address to a target one of the physical addresses based on the respective indexing, and performing data transfer operations with respect to the data storage location at the target physical address.