Scheme for securing locally generated data with authenticated write operations

• US 8,219,829 B2
• Filed: 12/08/2005
• Issued: 07/10/2012
• Est. Priority Date: 12/08/2005
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rudelic, John
• Primary Examiner(s): LEMMA, SAMSON B
• Application Number:
  US11/298,045
• Publication Number:
  US 20070136407A1
• Time in Patent Office: 2,406 Days
• Field of Search: 713/170, 713/193, 713/189, 709/223, 380/282, 726/26
• US Class Current: 713/193
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00

Abstract

A scheme for securing a locally generated data on a system using authenticated write operations is disclosed. According to an embodiment of the present invention, a private/public key pair is randomized and repeatedly generated to protect operations to data blocks.

Claims

1. A method comprising:

generating a private key and a corresponding public key upon system power up;

storing the corresponding public key in a flash device in said system;

securing a write operation to the flash device with the private key; and

wherein the private key and the corresponding public key protect writes to a first block of memory in the flash device and another private key and another corresponding public key, wherein said private key and another private key are different keys, protect writes to a second block of memory in the flash device.

2. The method as recited in claim 1, wherein the flash device uses the corresponding public key to verify the write operation.

3. The method as recited in claim 1, wherein securing the write operation comprises signing the write operation.

4. The method as recited in claim 1, wherein the private key and the corresponding public key comprise a random, non-predictable key pair.

5. The method as recited in claim 1, further comprising:

generating another private key and another corresponding public key;

replacing the public key with the other corresponding public key in the memory device; and

securing another write operation with the other private key.

6. The method as recited in claim 5, wherein the generating the private key and the generating the other private key occur at a predefined time interval.

7. The method as recited in claim 5, wherein the generating the private key and the generating the other private key occur at a random time interval.

8. The method as recited in claim 1, wherein the write operation comprises an update to flash file system data.

9. The method as recited in claim 1, wherein the write operation comprises a write to a block of memory.

10. A system comprising:

a processor to generate a private key and a corresponding public key upon system power up;

a flash device to store the corresponding public key;

an input port from coupled to the processor and the flash device;

wherein the processor further to secure a write operation to the flash device with the private key; and

wherein the private key and the corresponding public key protect writes to a first block of memory in the flash device and another private key, different from said private key, and another corresponding public key protect writes to a second block of memory in the flash device.

11. The system as recited in claim 10, wherein the memory device comprises a controller to use the corresponding public key to verify the write operation.

12. The system as recited in claim 10, wherein the processor signs the write operation to secure the write operation using the private key.

13. The system as recited in claim 10, wherein the private key and the corresponding public key comprise a random, non-predictable key pair.

14. The system as recited in claim 10, wherein the processor is further to generate another private key and another corresponding public key, replace the public key with the other corresponding public key in the memory device, and secure another write operation with the other private key.

15. The system as recited in claim 14, wherein the processor generates the private key and the other private key at a predefined time interval.

16. The system as recited in claim 14, wherein the processor generates the private key and the other private key at a random time interval.