Memory card and memory controller

• US 8,219,882 B2
• Filed: 05/21/2008
• Issued: 07/10/2012
• Est. Priority Date: 08/09/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Tamura, Takayuki, Shibuya, Hirofumi, Goto, Hiroyuki, Shiota, Shigemasa, Nakamura, Yasuhiro
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US12/125,042
• Publication Number:
  US 20080229164A1
• Time in Patent Office: 1,511 Days
• Field of Search: 714/763, 714/773, 365/201
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.

Claims

1. A memory storage device comprising:

a flash memory;

control means for controlling an operation of said flash memory; and

an interface unit configured to couple said control means to a host device,

wherein said memory storage device is configured such that, while a power supply voltage is supplied from the host device after completion of an initial operation of said memory storage device, said control means carries out a first error check operation to said flash memory in response to first control information stored in said flash memory, autonomously and irrespectively of the host device,

wherein said flash memory stores a predetermined error frequency value, and

wherein data of said flash memory can be corrected when an error frequency resulting from said first error check operation is equal to or less than said predetermined error frequency value.

2. The memory storage device according to claim 1, wherein said control means includes a register configured to store said predetermined error frequency value read from said flash memory.

3. The memory storage device according to claim 2,

wherein, in said initial operation of said memory storage device, said control means carries out a second error check operation to said flash memory in response to second control information stored in said flash memory, and

wherein said initial operation is carried out in response to starting of supply of said power supply voltage from the host device.

4. The memory storage device according to claim 3, wherein said first error check operation and said second error check operation use an error correction code stored in said flash memory.

5. The memory storage device according to claim 4, wherein said memory storage device is configured such that said error correction code is stored in said flash memory in response to a data storing instruction from the host device.

6. The memory storage device according to claim 5, wherein said control means is configured to carry out a data read error check operation to said flash memory using said error correction code in response to a data read operation, which is performed in response to receiving a read instruction from the host device.

7. The memory storage device according to claim 6, wherein when said control means is configured to detect an error in data read out from a first area of said flash memory in said first error check operation, said control means also being configured to write said read out data, whose error is corrected, to a second area of said flash memory.

8. A memory storage device comprising:

a flash memory;

control means for controlling an access operation to said flash memory; and

an interface circuit configured to couple said control means to a host device,

wherein said memory storage device is configured such that, while a power supply voltage is supplied from the host device after completion of an initial operation of said memory storage device, said control means carries out an error check operation to data stored in said flash memory one or more times, autonomously and irrespectively of the host device,

wherein said flash memory stores a predetermined error frequency value, and

wherein data of said flash memory can be corrected when an error frequency resulting from said error check operation is equal to or less than said predetermined error frequency value.

9. The memory storage device according to claim 8, wherein said control means includes a register configured to store said predetermined error frequency value read from said flash memory.

10. The memory storage device according to claim 9, wherein said control means is configured to carry out said error check operation when reading data from a first area of said flash memory in response to receiving a read instruction accompanied by address information specifying said first area of said flash memory from the host device.

11. The memory storage device according to claim 10,

wherein said control means is configured to control storing of data and an error correction code, which is generated in accordance with said data, to said flash memory in response to receiving a write instruction accompanied with said data from the host device, and

wherein said control means is configured to carry out said error check operation using said error correction code.