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System and method of identifying and preventing security violations within a computing system

  • US 8,220,045 B2
  • Filed: 10/08/2004
  • Issued: 07/10/2012
  • Est. Priority Date: 07/23/2004
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • monitoring on a core bus coupled to a processor core at least one of voltage levels, clock frequencies, hardware fault injection and test and debug activity associated with an electronic apparatus;

    identifying unauthorized manipulation of at least one of said voltage levels, clock frequencies, hardware fault injection and test and debug activity as a security violation; and

    preventing execution of an instruction within the processor core in response to the security violation.

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