Method and system for forming a capacitive micromachined ultrasonic transducer

• US 8,222,065 B1
• Filed: 10/02/2009
• Issued: 07/17/2012
• Est. Priority Date: 10/02/2009
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Smeys, Peter, Johnson, Peter, Percin, Gokhan
• Primary Examiner(s): Wojciechowicz, Edward
• Application Number:
  US12/587,139
• Time in Patent Office: 1,019 Days
• Field of Search: 257/416, 438/51, 438/381, 438/393, 438/396, 600/459
• US Class Current: 438/51
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide features. For a particular embodiment, the SOI wafer comprises a single crystal epitaxial layer, a buried oxide layer and a silicon layer, and the single crystal epitaxial layer is bonded to the planarized oxide features, after which the silicon layer and the buried oxide layer of the SOI wafer are removed, leaving the single crystal epitaxial layer bonded to the oxide layer.

Claims

1. A method comprising:

forming oxide features over a capacitive micromachined ultrasonic transducer (CMUT) control chip that is in or over a silicon wafer, the CMUT control chip configured to control a capacitive micromachined ultrasonic transducer;

planarizing the oxide features;

bonding a silicon-on-insulator (SOI) wafer to the planarized oxide features;

depositing a first metal layer over the silicon wafer and the CMUT control chip, wherein the first metal layer forms first and second plate couplers in electrical contact with the CMUT control chip;

depositing a second metal layer over the first metal layer, wherein the second metal layer forms a first plate of a CMUT capacitor, wherein the first plate is in electrical contact with the first plate coupler; and

depositing a third metal layer over the second metal layer, wherein the third metal layer forms a second plate of the CMUT capacitor, wherein the second plate is in electrical contact with the second plate coupler.

2. The method of claim 1, wherein at least some of the planarized oxide features are disposed between the first and second plates of the CMUT capacitor.

3. The method of claim 1, further comprising:

forming a passivation oxide layer and a passivation nitride layer over the first and second plate couplers prior to depositing the second and third metal layers.

4. The method of claim 3, further comprising:

fixating first and second vias through the passivation nitride layer and the passivation oxide layer to the first and second plate couplers, respectively; and

forming first and second conductive plugs in the vias;

wherein the first plate of the CMUT capacitor is formed in electrical contact with the first conductive plug; and

wherein the second plate of the CMUT capacitor is formed in electrical contact with the second conductive plug.

5. The method of claim 1, further comprising:

forming an oxide layer over the second metal layer;

wherein forming the oxide features comprises patterning the oxide layer.

6. The method of claim 1, wherein:

the SOI wafer comprises a single crystal silicon layer, a buried oxide layer, and a silicon layer;

bonding the SOI wafer to the planarized oxide features comprises bonding the single crystal silicon layer to the planarized oxide features; and

the method further comprises removing the silicon layer and the buried oxide layer of the SOI wafer, wherein the single crystal silicon layer remains bonded to the planarized oxide features.

7. The method of claim 6, wherein:

the second metal layer also forms an additional conductive portion separate from the first plate of the CMUT capacitor, the additional conductive portion in electrical contact with the second plate coupler; and

the method further comprises etching a via through the single crystal silicon layer to expose the additional conductive portion.

8. The method of claim 7, wherein depositing the third metal layer comprises depositing the third metal layer over the single crystal silicon layer and in the via.

9. A method comprising:

forming oxide features over a capacitive micromachined ultrasonic transducer (CMUT) control chip that is in or over a silicon wafer, the CMUT control chip configured to control a capacitive micromachined ultrasonic transducer;

fly cutting the oxide features to planarize the oxide features;

bonding a single crystal silicon layer of a silicon-on-insulator (SOI) wafer to the planarized oxide features, wherein the SOI wafer comprises the single crystal silicon layer, a buried oxide layer, and a silicon layer;

forming first and second plate couplers over the silicon wafer and in electrical contact with the CMUT control chip;

forming a first plate of a CMUT capacitor over the first and second plate couplers, wherein the first plate is in electrical contact with the first plate coupler; and

forming a second plate of the CMUT capacitor over the first plate, wherein the second plate is in electrical contact with the second plate coupler.

10. The method of claim 9, wherein at least some of the planarized oxide features are disposed between the first and second plates of the CMUT capacitor.

11. The method of claim 9, wherein forming the first and second plate couplers comprises:

depositing a metal layer over the silicon wafer and the CMUT control chip; and

etching the metal layer to form the first and second plate couplers.

12. The method of claim 11, further comprising:

forming a passivation oxide layer and a passivation nitride layer over the first and second plate couplers;

forming first and second vias through the passivation nitride layer and the passivation oxide layer to the first and second plate couplers, respectively; and

forming first and second conductive plugs in the vias;

wherein the first plate of the CMUT capacitor is formed in electrical contact with the first conductive plug; and

wherein the second plate of the CMUT capacitor is formed in electrical contact with the second conductive plug.

13. The method of claim 12, wherein forming the first plate of the CMUT capacitor comprises depositing a second metal layer over the passivation nitride layer.

14. The method of claim 13, further comprising:

removing the silicon layer and the buried oxide layer of the SOI wafer, wherein the single crystal silicon layer remains bonded to the planarized oxide features.

15. The method of claim 14, wherein:

forming the first plate of the CMUT capacitor comprises forming an additional conductive portion separate from the first plate of the CMUT capacitor, the additional conductive portion in electrical contact with the second plate coupler; and

the method further comprises etching a third via through the single crystal silicon layer to expose the additional conductive portion.

16. The method of claim 15, wherein forming the second plate of the CMUT capacitor comprises depositing a third metal layer over the single crystal silicon layer and in the third via.

17. The method of claim 9, further comprising:

forming the CMUT control chip in or over the silicon wafer.

18. A method comprising:

forming first and second plate couplers over a capacitive micromachined ultrasonic transducer (CMUT) control chip, the CMUT control chip configured to control a capacitive micromachined ultrasonic transducer;

forming a first plate of a CMUT capacitor over the first and second plate couplers, wherein the first plate is in electrical contact with the first plate coupler;

forming one or more oxide features over the first plate;

planarizing the one or more oxide features;

bonding a single crystal silicon layer of a silicon-on-insulator (SOI) wafer to the one or more planarized oxide features, wherein the SOI wafer comprises the single crystal silicon layer, a buried oxide layer, and a silicon layer;

removing the silicon layer and the buried oxide layer of the SOI wafer, wherein the single crystal silicon layer remains bonded to the one or more planarized oxide features; and

forming a second plate of the CMUT capacitor over the single crystal silicon layer, wherein the second plate is in electrical contact with the second plate coupler.

19. The method of claim 18, further comprising:

forming at least one passivation layer over the first and second plate couplers prior to forming the first and second plates;

forming first and second vias through the at least one passivation layer to the first and second plate couplers, respectively; and

forming first and second conductive plugs in the vias;

wherein the first plate is in electrical contact with the first conductive plug; and

wherein the second plate is in electrical contact with the second conductive plug.

20. The method of claim 19, further comprising:

etching a third via through the single crystal silicon layer;

wherein forming the second plate comprises depositing conductive material over the single crystal silicon layer and within the third via.