Method and system for template assisted wafer bonding

• US 8,222,084 B2
• Filed: 05/20/2011
• Issued: 07/17/2012
• Est. Priority Date: 12/08/2010
• Status: Active Grant

• Current Assignee: Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Dallesasse, John, Krasulick, Stephen B.
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/112,142
• Publication Number:
  US 20120149148A1
• Time in Patent Office: 424 Days
• Field of Search: 438/63, 257/E21.513
• US Class Current: 438/113
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1204 Optical Diode
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 31/1876 Particular processes or apparatus for batch treatment of the devices
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/48 characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/026 Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06

Abstract

A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the SOI substrate and the assembly substrate, joining the SOI substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Claims

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing an SOI substrate including a plurality of silicon-based devices;

providing a compound semiconductor substrate including a plurality of photonic devices;

dicing the compound semiconductor substrate to provide a plurality of photonic dies, each die including one or more of the plurality of photonics devices;

providing an assembly substrate;

mounting the plurality of photonic dies on predetermined portions of the assembly substrate;

aligning the SOI substrate and the assembly substrate;

joining the SOI substrate and the assembly substrate to form a composite substrate structure; and

removing at least a portion of the assembly substrate from the composite substrate structure.

2. The method of claim 1 wherein the plurality of silicon-based devices comprise CMOS devices.

3. The method of claim 1 wherein the plurality of silicon-based devices comprise at least one of a detector, a CCD, logic circuits, or emitter coupled logic circuits, BiCMOS circuits, NMOS circuits, PMOS circuits, or other silicon-based devices or circuits.

4. The method of claim 1 wherein the compound semiconductor substrate comprises a III-V wafer.

5. The method of claim 1 wherein the compound semiconductor substrate comprises a II-VI wafer.

6. The method of claim 1 wherein the plurality of photonic devices include at least one of a laser, a detector, or a modulator.

7. The method of claim 6 wherein the plurality of photonic devices further include at least one of imaging optics, magnetic materials, birefringent materials, or non-linear optical materials.

8. The method of claim 1 wherein the compound semiconductor substrate further includes electronic devices.

9. The method of claim 8 wherein the electronic devices include at least one of HBTs, HEMTs, or FETs.

10. The method of claim 1 wherein providing the assembly substrate comprises:

oxidizing a silicon substrate;

implanting the oxidized silicon substrate to form an implant region; and

patterning the implanted substrate to form the predetermined portions.

11. The method of claim 10 wherein implanting the oxidized silicon substrate comprises implanting at least one of hydrogen or helium.

12. The method of claim 10 wherein removing at least a portion of the assembly substrate comprises annealing the composite substrate structure to split the assembly substrate at the implant region.

13. The method of claim 10 wherein removing at least a portion of the assembly substrate comprises lapping the portion of the assembly substrate.

14. A method of growing a compound semiconductor structure on a silicon-based substrate, the method comprising:

providing an SOI base wafer having a bonding surface;

providing a seed wafer;

dicing the seed wafer to provide a plurality of seed dies;

providing a template wafer;

mounting the plurality of seed dies on the template wafer;

bonding the template wafer to the SOI base wafer, wherein the plurality of seed dies are joined to the bonding surface of the SOI base wafer;

removing at least a portion of the template wafer;

exposing at least a portion of a surface of the plurality of seed dies; and

growing the compound semiconductor structure on the exposed seed dies.

15. The method of claim 14 wherein growing the compound semiconductor structure comprises performing an epitaxial growth process.

16. The method of claim 14 wherein the SOI base wafer comprises doped regions associated with transistors.

17. The method of claim 14 wherein the seed wafer comprises a III-V wafer.

18. The method of claim 14 wherein mounting the plurality of seed dies to the template wafer comprises mounting the plurality of seed dies on predetermined regions of the template wafer.

19. The method of claim 14 wherein providing the template wafer comprises:

oxidizing a silicon substrate;

implanting a dopant into the oxidized silicon substrate to form an implant region; and

patterning the implanted substrate to form the predetermined portions.

20. The method of claim 19 wherein the implant region ranges from about 0.1 μ

m to about 5 μ

m from a surface of the template wafer.

21. The method of claim 20 wherein removing at least a portion of the template wafer comprises:

annealing the bonded template wafer and SOI base wafer; and

splitting the template wafer at the implant region.

22. The method of claim 21 further comprising performing a CMP process after splitting the template wafer.

23. The method of claim 14 further comprising at least one of fabricating gate metals or fabricating transistor interconnects after growing the compound semiconductor structure.

24. The method of claim 14 wherein exposing at least a portion of a surface of the plurality of seed dies comprises patterning and etching portions of the template wafer.

25. The method of claim 14 wherein bonding the template wafer to the SOI base wafer comprises forming at least one of a semiconductor-semiconductor bond or a metal assisted semiconductor bond.

26. The method of claim 25 wherein the metal assisted semiconductor bond comprises InPd.