Methods of fabricating a memory device

• US 8,222,105 B2
• Filed: 02/10/2010
• Issued: 07/17/2012
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Haller, Gordon, Tang, Sanh D., Cummings, Steve
• Primary Examiner(s): Picardat, Kevin M
• Assistant Examiner(s): PRASAD, NEIL R
• Application Number:
  US12/703,502
• Publication Number:
  US 20100144107A1
• Time in Patent Office: 888 Days
• Field of Search: 438/242, 438/288, 438/972, 438/253, 257/E21.646
• US Class Current: 438/253
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Claims

1. A method of fabricating a memory device, the method comprising;

forming a semiconductor substrate having a first surface;

forming a recessed gate in the substrate, wherein the recessed gate defines first and second lateral sides;

forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;

forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;

forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region; and

forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate, wherein the conductive data line is formed to electrically and directly physically contact the second source/drain region in the absence of any separately formed conductive plug extending between the second source/drain region and the conductive data line in a completed construction of the memory device.

2. The method of claim 1 comprising forming the first and second source/drain regions to have coplanar upper surfaces in the completed construction of the memory device.

3. The method of claim 1 comprising forming the charge storage device to comprise a capacitor.

4. The method of claim 1 comprising forming the capacitor to comprise:

a storage node;

a dielectric substantially surrounding the storage node; and

a top cell plate substantially surrounding the dielectric.

5. The method of claim 1 comprising forming the conductive data line to comprise polysilicon.

6. The method of claim 1 comprising forming the conductive data line to comprise silicide.

7. The method of claim 1 comprising forming the conductive data line to comprise polysilicon and silicide.

8. The method of claim 1 comprising forming an upper surface of the gate to be elevationally below upper surfaces of each of the first and second source/drain regions.

9. The method of claim 8 comprising forming the upper surface of the gate to be elevationally closer to a lower surface of the second source/drain than to the second source/drain upper surface in the completed construction of the memory device.

10. The method of claim 1 comprising forming an upper surface of the gate to be elevationally closer to lower surfaces of each of the first and second source/drain than to the first surface in the completed construction of the memory device.

11. The method of claim 1 comprising forming a gate dielectric in contact with the recessed gate and to extend along the first and second lateral sides, and forming the gate dielectric to have an uppermost surface which is co-planar with the upper surfaces of each of the first and second source/drain in the completed construction of the memory device.

12. A method of fabricating a memory device, the method comprising;

forming a semiconductor substrate having a first surface;

forming a recessed gate in the substrate, wherein the recessed gate defines first and second lateral sides;

forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;

forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;

depositing dielectric material over the recessed gate and the second source/drain region;

forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region through the dielectric material; and

forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate, wherein the conductive data line is formed to electrically and directly physically contact the second source/drain region in the absence of any separately formed conductive plug extending between the second source/drain region and the conductive data line in a completed construction of the memory device.

13. The method of claim 12 wherein the dielectric material comprises oxide.

14. The method of claim 12 wherein the dielectric material comprises silicon dioxide.

15. The method of claim 12 comprising forming the conductive data line to comprise polysilicon.

16. The method of claim 12 comprising forming the conductive data line to comprise silicide.

17. The method of claim 12 comprising forming the conductive data line to comprise polysilicon and silicide.

18. The method of claim 12 comprising forming an upper surface of the gate to be elevationally below upper surfaces of each of the first and second source/drain regions.

19. The method of claim 18 comprising forming the upper surface of the gate to be elevationally closer to a lower surface of the second source/drain than to the second source/drain upper surface in the completed construction of the memory device.

20. The method of claim 12 comprising forming an upper surface of the gate to be elevationally closer to lower surfaces of each of the first and second source/drain than to the first surface in the completed construction of the memory device.

21. The method of claim 12 comprising forming a gate dielectric in contact with the recessed gate and to extend along the first and second lateral sides, and forming the gate dielectric to have an uppermost surface which is co-planar with the upper surfaces of each of the first and second source/drain in the completed construction of the memory device.