Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously

• US 8,222,139 B2
• Filed: 03/30/2010
• Issued: 07/17/2012
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Lin, I-Ching
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US12/750,364
• Publication Number:
  US 20110244676A1
• Time in Patent Office: 840 Days
• Field of Search: 438/667, 438/672, 438/675, 257/E21.577
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10

Abstract

A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.

Claims

1. A method of forming a through-silicon via (TSV) structure, comprising:

providing a semiconductor substrate having a first region and a second region;

forming a dielectric layer on the semiconductor substrate, wherein the dielectric layer comprises a first opening in the first region;

forming a first conductive material layer on the dielectric layer, filling the first opening;

forming a second opening in the second region extending through the first conductive material layer, the dielectric layer and a portion of the semiconductor substrate, wherein the second opening has a sidewall portion and a bottom portion;

forming a passivation layer overlying the first conductive material layer and lining the sidewall portion and the bottom portion of the second opening;

forming a second conductive material layer overlying the passivation layer, filling the second opening; and

removing portions of the second conductive material layer, the passivation layer and the first conductive material layer positioned outside the first opening and the second opening to expose the dielectric layer, wherein a portion of the second conductive material layer remaining in the second opening forms the TSV structure.

2. The method of claim 1, wherein said removing is performed by a chemical mechanical polishing (CMP) process.

3. The method of claim 1, wherein the portion of the first conductive material layer remaining in the first opening forms a contact plug.

4. The method of claim 1, further comprising:

forming an integrated circuit (IC) component on the semiconductor substrate before forming a dielectric layer on the semiconductor substrate,

wherein the first opening exposes the IC component.

5. The method of claim 1, wherein the first conductive material layer comprises tungsten, tungsten alloy, copper, or copper alloy.

6. The method of claim 1, wherein the second conductive material layer comprises copper, or copper alloy.

7. The method of claim 1, wherein the passivation layer comprises oxide.

8. The method of claim 1, further comprising:

forming a barrier layer on the passivation layer before forming the second conductive material layer.

9. The method of claim 8, wherein the barrier layer comprises Ti, Ta, TiN, or TaN.

10. The method of claim 1, wherein:

the dielectric layer is an inter-layer dielectric (ILD) layer comprising at least one selected from the group consisting of

a silicon oxide containing layer formed of doped or undoped silicon oxide,

doped or P-doped spin-on-glass (SOG),

Phosphorus-doped Tetraethoxy Silane (PTEOS), and

Boron-Phosphosilicate Tetraethoxy Silane (BPTEOS); and

the first conductive material layer is formed directly on the ILD layer.