Semiconductor device and method of manufacturing the same

• US 8,222,649 B2
• Filed: 11/17/2006
• Issued: 07/17/2012
• Est. Priority Date: 02/07/2006
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Miura, Naruhisa, Fujihira, Keiko, Otsuka, Kenichi, Imaizumi, Masayuki
• Primary Examiner(s): Bryant, Kiesha
• Assistant Examiner(s): WARD, ERIC A
• Application Number:
  US12/161,592
• Publication Number:
  US 20100219417A1
• Time in Patent Office: 2,069 Days
• Field of Search: 257/77, 257/134, 257/135, 257/262, 257/287, 257327-346, 257/404, 257/496, 257/E29.104
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.

Claims

1. A semiconductor device comprising:

a substrate formed of silicon carbide including a first conductivity type impurity;

a first drift layer formed of silicon carbide including a first conductivity type impurity of first concentration, being disposed entirely on a surface of said substrate;

a second drift layer formed of silicon carbide including a first conductivity type impurity of second concentration higher than said first concentration, being disposed on a surface of said first drift layer;

a plurality of well regions containing a second conductivity type impurity, being disposed in said second drift layer;

a current control region disposed in second drift layer between a pair of said well regions;

a gate electrode disposed above said current control region; and

a gate insulating film disposed between said gate electrode and said current control region,

wherein the concentration of the first conductivity type impurity of said second drift layer varies in a region having a depth no greater than a depth of said well region from a surface of said second drift layer in accordance with the depth from said surface of said second drift layer, said depth comprising the distance from said gate electrode, and

wherein said region in which the concentration of the first conductivity type impurity of said second drift layer varies includes a region in said well region in which a channel is formed.

2. The semiconductor device according to claim 1, wherein

the concentration of the first conductivity type impurity of said second drift layer becomes lower as said depth increases and continuously coincides with the concentration of the first conductivity type impurity of said first drift layer at an interface with said first drift layer.

3. The semiconductor device according to claim 1, wherein

the concentration of the first conductivity type impurity of said second drift layer becomes higher as said depth increases, and

the concentrations of the first conductivity type impurity of said first and second drift layers discontinuously change at an interface between said first and second drift layers.

4. The semiconductor device according to claim 1, wherein

the concentration of the second conductivity type impurity implanted into said well regions is lower than the concentration of the first conductivity type impurity of said second drift layer at a surface portion of said well region.

5. The semiconductor device according to claim 1, wherein

the concentration of the second conductivity type impurity implanted into said well regions is higher than the concentration of the first conductivity type impurity of said second drift layer at a surface portion of said well region.

6. The semiconductor device according to claim 1, wherein

said second drift layer is disposed entirely on a surface of said first drift layer except its vicinity of outer peripheral portion, and

a step portion at an end portion adjacent to said vicinity of outer peripheral portion of said second drift layer has a tapered shape.

7. The semiconductor device according to claim 6, wherein

said plurality of well regions includes

a first well region disposed continuously from the end portion adjacent to said vicinity of outer peripheral portion of said second drift layer to a portion of said first drift layer below said vicinity of outer peripheral portion;

and

a second well region disposed in said second drift layer except the end portion adjacent to said vicinity of outer peripheral portion, and

said first well region is extended toward the outside of said step portion.

8. The semiconductor device according to claim 1, further comprising

an extension region containing a first conductivity type impurity having a concentration higher than said second concentration, being disposed at each of respective interfaces between said current control region and said well regions in a surface of said second drift layer.

9. The semiconductor device according to claim 8, wherein

said extension region is shallower than said well regions and said current control region.