Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof

• US 8,222,690 B2
• Filed: 10/12/2010
• Issued: 07/17/2012
• Est. Priority Date: 08/26/2005
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ohtani, Kinya, Kobayashi, Kenya
• Primary Examiner(s): HUBER, ROBERT T
• Application Number:
  US12/923,859
• Publication Number:
  US 20110024832A1
• Time in Patent Office: 644 Days
• Field of Search: 257/328, 257/329, 257/330, 257/331, 257/E27.02, 257/E29.183, 257/E29.262
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions.

Claims

1. A semiconductor apparatus, comprising:

a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type;

a first gate trench formed in the semiconductor layer; and

a second gate trench formed in the semiconductor layer separated from the first gate trench in a first direction,

wherein the doped semiconductor layer comprises;

a low concentration base region of a second conductivity typed formed between the first and second gate trenches, the low concentration base region having a first edge in touch with the first gate trench and a second edge in touch with the second gate trench;

a first source region of the first conductivity type formed at an upper surface of the low concentration base region;

a second source region of the first conductivity type formed at the upper surface of the low concentration base region separated from the first source region in a second direction perpendicular to the first direction, each of the first and second source regions having a first edge in touch with the first gate trench and a second edge in touch with the second gate trench;

a first high concentration base region of the second conductivity type formed at an upper surface of the low concentration base region between the first and second source regions, the first high concentration base region comprising a first edge in touch with the first gate trench, a second edge in touch with the second gate trench, a third edge in touch with the first source region, and a fourth edge in touch with the second source region;

a second high concentration base region of the second conductivity type formed below the first high concentration base region, and in a third direction perpendicular to both the first direction and the second direction, so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not provided below both of the first and second source regions; and

a third high concentration base region of the second conductivity type formed between the first and second high concentration base regions so that the first and third high concentration base regions are separated by the low concentration base region, the third and second high concentration base regions are separated by the low concentration base region, and the third high concentration base region is not provided below both of the first and second source regions.

2. The semiconductor apparatus according to claim 1, wherein the second high concentration base region comprises a first edge in touch with the first gate trench and a second edge in touch with the second gate trench.

3. The semiconductor apparatus according to claim 1, wherein the third high concentration base region comprises a first edge in touch with the first gate trench and a second edge in touch with the second gate trench.