Gate pullback at ends of high-voltage vertical transistor structure

• US 8,222,691 B2
• Filed: 08/25/2009
• Issued: 07/17/2012
• Est. Priority Date: 02/16/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Parthasarathy, Vijay, Manley, Martin H.
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US12/583,745
• Publication Number:
  US 20090315105A1
• Time in Patent Office: 1,057 Days
• Field of Search: 257328-342, 257/488, 257/E29.26, 257/E29.262
• US Class Current: 257/331
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Claims

1. A high-voltage transistor comprising:

a pillar of semiconductor material arranged on a die in an annular layout having first and second substantially linear portions that extend in a first lateral direction and first and second rounded end portions that connect the first and second substantially linear portions at respective opposite ends of the annular layout, the pillar including a drift region that extends in a vertical direction through the die;

first and second dielectric regions disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions;

first and second gate members respectively disposed in the first and second dielectric regions on opposite sides of the first substantially linear portion of the pillar;

third and fourth gate members respectively disposed in the first and second dielectric regions on opposite sides of the second substantially linear portion of the pillar; and

wherein the first, second, third, and fourth gate members terminate at or near the first and second rounded end portions such that the first and second rounded end portions are devoid of gate members.

2. The high-voltage transistor of claim 1 further comprising a gate metal bus that extends in a second lateral direction orthogonal to the first lateral direction, the gate metal bus being electrically connected to the first, second, third, and fourth gate members.

3. The high-voltage transistor of claim 1 wherein a length of the substantially linear section in the first lateral direction is at least 30 times greater than a width of the annular layout in a second lateral direction orthogonal to the first lateral direction.

4. The high-voltage transistor of claim 1 wherein the first, second, third, and fourth gate members are completely insulated from the first and second field plates.

5. The high-voltage transistor of claim 1 wherein the pillar further includes a source region disposed at or near a top surface of the pillar, and a body region that separates the source region from the drift region.

6. The high-voltage transistor of claim 5 wherein the first, second, third, and fourth gate members are each disposed adjacent the body region and separated from the body region by a gate oxide.