Trench-gate transistors and their manufacture

• US 8,222,693 B2
• Filed: 03/03/2008
• Issued: 07/17/2012
• Est. Priority Date: 03/10/2004
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Koops, Gerrit E. J., In't Zandt, Michael Antoine Armand
• Primary Examiner(s): REAMES, MATTHEW L
• Application Number:
  US12/041,117
• Publication Number:
  US 20080150021A1
• Time in Patent Office: 1,597 Days
• Field of Search: 257/335, 257/E29.027, 257/E29.066, 257/E29.256, 257/E29.257, 257/E29.26, 257/E21.417, 257/E21.418
• US Class Current: 257/335
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick gate electrode and the integral first layer also provides a first part of a stack of materials which constitute a thick trench sidewall insulating layer for a thin field plate. Consistent with an example embodiment, there is a method of manufacture. A hardmask used to etch the trenches is removed before providing the silicon dioxide layer. The layer is then protected by successive selective etching of the oxide layer and the nitride layer in the upper parts of the trenches. After the gate electrodes are provided, layers for the channel accommodating regions and source regions may be formed through the oxide layer on the upper surface.

Claims

1. A transistor circuit comprising:

a semiconductor body;

a plurality of transistor cells in the body, each cell having a channel region in the body and, underlying the channel region, a drain drift region;

an array of trenches extending from an upper surface of the semiconductor body, each trench extending through one of the channel regions and into an underlying drain drift region; and

in each trench,

a gate dielectric insulating layer extending from an upper surface of the semiconductor body, over a top corner of the trench and along a sidewall of the trench adjacent to both the channel region and the drain drift region;

a layer of silicon nitride laterally adjacent a portion of the gate dielectric insulating layer that is adjacent the drain drift region;

a layer of silicon dioxide laterally adjacent a portion of the gate dielectric insulating layer that is adjacent the drain drift region;

a gate immediately laterally adjacent a portion of the gate dielectric insulating layer that is adjacent the channel region; and

a field plate below the gate and separated from a portion of the gate dielectric insulating layer that is adjacent the drain drift region by the respective layers of silicon nitride and silicon dioxide.

2. The circuit of claim 1, wherein the gate and the field plate form a contiguous conductive material in the trench.

3. The circuit of claim 1, wherein the drain drift region underlies the channel region.

4. The circuit of claim 1, wherein the drain drift region is shared by a plurality of the cells.

5. The circuit of claim 1, wherein the field plate is configured to effect an electrical field in the drain drift region of a transistor, the electrical field being substantially uniform in an off state of the transistor.

6. The circuit of claim 1, wherein the drain drift region includes a doped region having a higher concentration of dopants adjacent the trench, relative to regions of the drain drift region that are further away from the trench.

7. The circuit of claim 1,

each cell further including a source region over the channel region and separated from the drain drift region by the channel region, and

wherein, for each cell, the gate is configured to bias the channel region, in response to a voltage potential applied to the gate, to form a vertical conduction channel extending between the source region and the drain region underlying the channel region.