Hybrid integrated circuit device and electronic device

• US 8,222,734 B2
• Filed: 11/29/2011
• Issued: 07/17/2012
• Est. Priority Date: 02/06/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Moriyama, Shinji, Yamada, Tomio
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US13/306,347
• Publication Number:
  US 20120106110A1
• Time in Patent Office: 231 Days
• Field of Search: 257/698, 257/700, 257/724, 257/774, 257/787, 257/E21.597
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03G 3/3042 : in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H05K 1/0263 : High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2201/099 : Coating over pads, e.g. solder resist partly over pads
• CPC Class Codes: H05K 2201/09909 : Special local insulating pattern, e.g. as dam around component
• CPC Class Codes: H05K 2201/10371 : Shields or metal cases
• CPC Class Codes: H05K 3/3405 : Edge mounted components, e.g. terminals
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3452 : Solder masks

Abstract

A hybrid integrated circuit device having high mount reliability includes a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Claims

1. An electronic device comprising:

a wiring substrate having an obverse surface, a reverse surface opposite to the obverse surface, a plurality of first land pads formed over the obverse surface, and a plurality of second land pads formed over the reverse surface, and a third land pad formed over the reverse surface, and parts of the plurality of first land pads are electrically connected to parts of the plurality of second land pads;

a semiconductor chip mounted over the obverse surface of the wiring substrate having a top surface, a bottom surface opposite to the top surface, and a plurality of pads formed over the top surface, the plurality of pads are electrically connected to the plurality of first land pads of the wiring substrate via a plurality of wires, respectively, and the bottom surface is electrically connected to the third land pad of the wiring substrate;

a plurality of passive components mounted on the obverse surface of the wiring substrate and connected to the wiring substrate electrically; and

a sealing body sealing the semiconductor chip and the plurality of wires;

wherein the plurality of the second land pads are disposed over the bottom surface of the wiring substrate such that the second land pads of the plurality of the second land pads surround the third land pad,

wherein the third land pad is divided into a plurality of regions, and

wherein an area of one of the plurality of regions of the third land pad is larger than an area of one of the plurality of second land pads.

2. The electronic device according to claim 1,

wherein the plurality of second land pads are disposed along sides of the wiring substrate.

3. The electronic device according to claim 1,

wherein the bottom surface of the semiconductor chip is connected to the third land pad via metal via holes.