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Low power digital phase lock loop circuit

  • US 8,222,933 B2
  • Filed: 05/07/2010
  • Issued: 07/17/2012
  • Est. Priority Date: 05/07/2010
  • Status: Active Grant
First Claim
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1. A digital phase lock loop circuit for use with a reference clock signal, said digital phase lock loop circuit comprising:

  • a phase detecting portion operable to output a compared signal based on the reference clock signal;

    an oscillator operable to output an oscillator clock signal;

    a feedback divider operable to output a divided signal based on the oscillator clock signal;

    a switching portion operable to output a first feedback signal based on the oscillator clock signal when in a first state, to output a second feedback signal based on the divided signal when in a second state and to switch from the first state to the second state,wherein said phase detecting portion is further operable to receive a first input feedback signal, based on the first feedback signal, when said switching portion is in the first state, andwherein said phase detecting portion is further operable to receive a second input feedback signal, based on the second feedback signal, when said switching portion is in the second state,wherein said phase detecting portion comprises a first flip-flop, a second flip-flop, an AND gate and a switch,wherein said first flip-flop is arranged to receive a VDD input, the reference clock signal and a clear signal and is operable to output an UP pulse,wherein said second flip-flop is arranged to receive an enable input, to receive the first input feedback signal when said switching portion is in the first state, to receive the second input feedback signal when said switching portion is in the second state and the clear signal and is operable to output a DOWN pulse,wherein said AND gate is arranged to receive the UP pulse and the DOWN pulse and is operable to output the clear signal, andwherein said switch is arranged to receive the DOWN pulse and is operable to output the DOWN pulse when said switching portion is in the first state and to not output the DOWN pulse when said switching portion is in the second state.

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