Low power digital phase lock loop circuit

• US 8,222,933 B2
• Filed: 05/07/2010
• Issued: 07/17/2012
• Est. Priority Date: 05/07/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Nagaraj, Krishnaswamy
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Cole, Brandon S
• Application Number:
  US12/775,527
• Publication Number:
  US 20110273210A1
• Time in Patent Office: 802 Days
• Field of Search: 327/141, 327144-163, 331/1.A, 331 15- 17, 375373-376
• US Class Current: 327/147
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence

Abstract

A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next oscillator clock edge rather than a feedback clock edge. This technique can be used to significantly reduce digital phase lock loop circuit power by disabling feedback divider and sync FF once initial frequency lock is established, provided phase jitter of digital phase lock loop circuit is low enough so that there is no cycle slip. This technique can also be used to multiply the effective reference clock frequency of digital phase lock loop circuits to increases the loop bandwidth, thus reducing the phase noise. Both the applications of this technique can be combined in some circuits.

Claims

1. A digital phase lock loop circuit for use with a reference clock signal, said digital phase lock loop circuit comprising:

a phase detecting portion operable to output a compared signal based on the reference clock signal;

an oscillator operable to output an oscillator clock signal;

a feedback divider operable to output a divided signal based on the oscillator clock signal;

a switching portion operable to output a first feedback signal based on the oscillator clock signal when in a first state, to output a second feedback signal based on the divided signal when in a second state and to switch from the first state to the second state,

wherein said phase detecting portion is further operable to receive a first input feedback signal, based on the first feedback signal, when said switching portion is in the first state, and

wherein said phase detecting portion is further operable to receive a second input feedback signal, based on the second feedback signal, when said switching portion is in the second state,

wherein said phase detecting portion comprises a first flip-flop, a second flip-flop, an AND gate and a switch,

wherein said first flip-flop is arranged to receive a VDD input, the reference clock signal and a clear signal and is operable to output an UP pulse,

wherein said second flip-flop is arranged to receive an enable input, to receive the first input feedback signal when said switching portion is in the first state, to receive the second input feedback signal when said switching portion is in the second state and the clear signal and is operable to output a DOWN pulse,

wherein said AND gate is arranged to receive the UP pulse and the DOWN pulse and is operable to output the clear signal, and

wherein said switch is arranged to receive the DOWN pulse and is operable to output the DOWN pulse when said switching portion is in the first state and to not output the DOWN pulse when said switching portion is in the second state.

2. The digital phase lock loop circuit of claim 1,

wherein said phase detecting portion is further to operable to output the compared signal based on the reference clock signal and the first input feedback signal when said switching portion is in the first state, and

wherein said phase detecting portion is further to operable to output the compared signal based on the reference clock signal and the second input feedback signal when said switching portion is in the second state.

3. The digital phase lock loop circuit of claim 2, further comprising a time-to-digital portion operable to output a digital delay signal based on the compared signal.

4. The digital phase lock loop circuit of claim 3, further comprising:

a loop filter portion operable to output a filtered delay signal based on the digital delay signal,

wherein said oscillator is operable to output the oscillator clock signal based on the filtered delay signal.

5. The digital phase lock loop circuit of claim 4, further comprising:

a synchronization flip-flop operable to output a synchronized signal based on the oscillator clock signal and the divided signal,

wherein said switching portion is operable to output the second feedback signal based on the synchronized signal when in a second state.

6. The digital phase lock loop circuit of claim 5, further comprising a lock detector portion operable to detect a parameter based on the reference clock and to switch said switching portion from the first state to the second state based on the detected parameter.

7. The digital phase lock loop circuit of claim 6, further comprising:

an input divider operable to output a select signal; and

an output divider operable to output a divided output signal.

8. The digital phase lock loop circuit of claim 7, further comprising an error corrector operable to output a corrected digital delay signal based on the digital delay signal and the select signal.

9. The digital phase lock loop circuit of claim 1, further comprising:

an input divider operable to output a select signal; and

an output divider operable to output a divided output signal.

10. The digital phase lock loop circuit of claim 9, further comprising an error corrector operable to output a corrected digital delay signal based on the digital delay signal and the select signal.

11. The digital phase lock loop circuit of claim 10,

wherein said error corrector comprises a demultiplexer, an averager, an adder and a multiplexer,

wherein said demultiplexer is arranged to receive the digital delay signal and the select signal, and is operable to output a first phase difference signal and a second phase difference signal based on the select signal,

wherein said averager is operable to receive the second phase difference signal and to output an expected phase difference signal based on the second phase difference signal,

wherein said adder is operable to output a residual phase difference signal based on the second phase difference signal and the expected phase difference signal, and

wherein said multiplexer is operable to output, based on the select signal, a corrected digital delay signal based on the first phase difference signal and the residual phase difference signal.

12. A digital phase lock loop circuit for use with a reference clock signal, said digital phase lock loop circuit comprising:

a phase detecting portion operable to output a compared signal based on the reference clock signal;

an oscillator operable to output an oscillator clock signal;

a feedback divider operable to output a divided signal based on the oscillator clock signal;

a switching portion operable to output a first feedback signal based on the oscillator clock signal when in a first state, to output a second feedback signal based on the divided signal when in a second state and to switch from the first state to the second state;

a time-to-digital portion operable to output a digital delay signal based on the compared signal;

a loop filter portion operable to output a filtered delay signal based on the digital delay signal;

a synchronization flip-flop operable to output a synchronized signal based on the oscillator clock signal and the divided signal;

a lock detector portion operable to detect a parameter based on the reference clock and to switch said switching portion from the first state to the second state based on the detected parameter;

an input divider operable to output a select signal;

an output divider operable to output a divided output signal; and

an error corrector operable to output a corrected digital delay signal based on the digital delay signal and the select signal,

wherein said phase detecting portion is further operable to receive a first input feedback signal, based on the first feedback signal, when said switching portion is in the first state,

wherein said phase detecting portion is further operable to receive a second input feedback signal, based on the second feedback signal, when said switching portion is in the second state,

wherein said phase detecting portion is further to operable to output the compared signal based on the reference clock signal and the first input feedback signal when said switching portion is in the first state,

wherein said phase detecting portion is further to operable to output the compared signal based on the reference clock signal and the second input feedback signal when said switching portion is in the second state,

wherein said oscillator is operable to output the oscillator clock signal based on the filtered delay signal,

wherein said switching portion is operable to output the second feedback signal based as the synchronized signal when in a second state,

wherein said error corrector comprises a demultiplexer, an averager, an adder and a multiplexer,

wherein said demultiplexer is arranged to receive the digital delay signal and the select signal, and is operable to output a first phase difference signal and a second phase difference signal based on the select signal,

wherein said averager is operable to receive the second phase difference signal and to output an expected phase difference signal based on the second phase difference signal,

wherein said adder is operable to output a residual phase difference signal based on the second phase difference signal and the expected phase difference signal, and

wherein said multiplexer is operable to output, based on the select signal, a corrected digital delay signal based on the first phase difference signal and the residual phase difference signal.

13. A method of digitally phase locking an output signal with a reference clock signal, said method comprising:

outputting, by way of a phase detecting portion, a compared signal based on the reference clock signal;

outputting, by way of an oscillator, an oscillator clock signal;

outputting, by way of a feedback divider, a divided signal based on the oscillator clock signal;

outputting, by way of a switching portion, a first feedback signal based on the oscillator clock signal when the switching portion is in a first state;

outputting, by way of the switching portion, a second feedback signal based on the divided signal when the switching portion is in a second state;

switching the switching portion from the first state to the second state;

receiving, at an input of the phase detecting portion, a first input feedback signal;

based on the first feedback signal, when the switching portion is in the first state;

receiving, at the input of the phase detecting portion, a second input feedback signal, based on the second feedback signal, when the switching portion is in the second state;

outputting, by way of an input divider, a select signal; and

outputting, by way of an output divider, a divided output signal.

14. The method of claim 13,

wherein said outputting a compared signal based on the reference clock signal comprises outputting the compared signal based on the reference clock signal and the first input feedback signal when the switching portion is in the first state, and

wherein said outputting a compared signal based on the reference clock signal further comprises outputting the compared signal based on the reference clock signal and the second input feedback signal when the switching portion is in the second state.

15. The method of claim 14, further comprising outputting, by way of a time-to-digital portion, a digital delay signal based on the compared signal.

16. The method of claim 15, further comprising:

outputting, by way of a loop filter portion, a filtered delay signal based on the digital delay signal,

wherein said outputting an oscillator clock signal comprises outputting the oscillator clock signal based on the filtered delay signal.

17. The method of claim 16, further comprising:

outputting, by way of a synchronization flip-flop, a synchronized signal based on the oscillator clock signal and the divided signal,

wherein said outputting a second feedback signal based on the divided signal when the switching portion is in a second state comprises outputting the second feedback signal based on the synchronized signal when in a second state.

18. The method of claim 17, further comprising:

detecting, by way of a lock detector portion, a parameter based on the reference clock,

wherein said switching the switching portion from the first state to the second state comprises switching the switching portion from the first state to the second state based on the detected parameter.