Receiver equalizer circuitry having wide data rate and input common mode voltage ranges

• US 8,222,967 B1
• Filed: 12/22/2009
• Issued: 07/17/2012
• Est. Priority Date: 12/22/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Raman, Sangeeta, Hoang, Tim Tri, Shumarayev, Sergey Yuryevich
• Primary Examiner(s): Jones, Stephen
• Application Number:
  US12/644,128
• Time in Patent Office: 938 Days
• Field of Search: 333/28.R, 333/18, 375/229, 375/230, 375/232, 375/233
• US Class Current: 333/28.R
• CPC Class Codes: H03F 2200/405 the output amplifying stage of an amplifier comprising more than three power stages
• CPC Class Codes: H03F 2203/45488 the CSC being a pi circuit and a capacitor being used at the place of the resistor
• CPC Class Codes: H03F 2203/45494 the CSC comprising one or more potentiometers
• CPC Class Codes: H03F 2203/45686 the LC comprising one or more potentiometers, which are not shunting potentiometers
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03H 11/1213 using transistor amplifiers H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/48 simulating reactances

Abstract

Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.

Claims

1. Equalizer circuitry on an integrated circuit (“

IC”

) comprising;

a plurality of NMOS equalizer stages connected in series;

a PMOS equalizer stage connected in parallel with the NMOS equalizer stage that is first in the series; and

control circuitry for determining whether the PMOS equalizer stage or the NMOS equalizer stage that is first in the series will be used.

2. The equalizer circuitry defined in claim 1 wherein the control circuitry controls whether or not each of the PMOS equalizer stage and the NMOS equalizer stage that is first in the series receives electrical power required for operation of that stage.

3. The equalizer circuitry defined in claim 1 wherein each of the NMOS equalizer stages and the PMOS equalizer stage comprise differential circuitry.

4. The equalizer circuitry defined in claim 1 wherein the plurality comprises four NMOS equalizer stages.

5. The equalizer circuitry defined in claim 1 wherein an output signal of the NMOS equalizer stage that is last in the series is connected to clock and data recovery (“

CDR”

) circuitry on the IC.

6. The equalizer circuitry defined in claim 1 wherein the control circuitry comprises memory circuitry on the IC.

7. The equalizer circuitry defined in claim 6 wherein the memory circuitry is programmable.

8. The equalizer circuitry defined in claim 1 wherein at least one of the NMOS equalizer stages comprises:

controllably variable capacitor circuitry; and

folded active inductor circuitry.

9. The equalizer circuitry defined in claim 8 wherein the at least one of the NMOS equalizer stages further comprises:

an NMOS transistor having a source-drain path connected in series between the folded active inductor circuitry and the controllably variable capacitor circuitry in the at least one of the NMOS equalizer stages, wherein a signal to be equalized by the at least one of the NMOS equalizer stages is applied to a gate of the NMOS transistor, and wherein an equalized output signal is derived from a node on the source-drain path of the NMOS transistor.

10. The equalizer circuitry defined in claim 9 wherein the at least one of the NMOS equalizer stages further comprises:

a source of power supply voltage;

a controllably variable resistor connected in series between the source of power supply voltage and a first end of the source-drain path of the NMOS transistor;

a source of ground voltage; and

a controllably variable current source connected in series between a second end of the source-drain path of the NMOS transistor and the source of ground voltage.

11. The equalizer circuitry defined in claim 10 wherein the at least one of the NMOS equalizer stages further comprises:

a further controllably variable resistor connected in parallel with the controllably variable capacitor circuitry; and

a further controllably variable current source in the folded active inductor circuitry of the at least one of the NMOS equalizer stages.

12. The equalizer circuitry defined in claim 11 further comprising:

memory circuitry on the IC for controlling at least one of the controllably variable capacitor, the controllably variable resistor, the controllably variable current source, the further controllably variable resistor, and the further controllably variable current source.

13. The equalizer circuitry defined in claim 12 wherein the memory circuitry is programmable.

14. Equalizer circuitry on an integrated circuit (“

IC”

) comprising;

a plurality of NMOS equalizer stages connected in series, wherein each of the NMOS equalizer stages is programmable to control at least one of bandwidth and power consumption of the equalizer circuitry, and wherein each of the equalizer stages comprises folded active inductor circuitry.

15. The equalizer circuitry defined in claim 14 wherein each NMOS equalizer stage comprises a controllably variable current source.

16. The equalizer circuitry defined in claim 14 wherein each equalizer stage comprises:

first and second circuit legs connected in parallel with one another between a power supply voltage source and ground; and

wherein the folded active inductor circuitry is connected between the circuit legs.

17. The equalizer circuitry defined in claim 14 further comprising:

a PMOS equalizer stage connected in parallel with the NMOS equalizer stage that is first in the series; and

control circuitry for determining whether the PMOS equalizer stage or the NMOS equalizer stage that is first in the series will be used, wherein each of the NMOS equalizer stages comprises;

first and second circuit legs connected in parallel with one another between a power supply voltage source and ground, each of the circuit legs including a source-drain path of an NMOS transistor, a controllably variable resistor connected in series between the power supply voltage source and a first end of the source-drain path, and a controllably variable current source connected in series between a second end of the source-drain path and ground;

a controllably variable capacitor connected between the circuit legs; and

a further controllably variable resistor connected between the circuit legs.

18. The equalizer circuitry defined in claim 17 wherein the PMOS equalizer stage comprises differential circuitry.

19. The equalizer circuitry defined in claim 17 further comprising:

memory circuitry on the IC for controlling at least one of the control circuitry, the controllably variable resistors, the controllably variable current sources, the controllably variable capacitors, and the further controllably variable resistors.

20. The equalizer circuitry defined in claim 19 wherein the memory circuitry is programmable.

21. The equalizer circuitry defined in claim 17 wherein each of the NMOS equalizer stages further comprises:

folded active inductive circuitry connected between first and second nodes that are respectively in the first and second circuit legs between the controllably variable resistor and the source-drain path in the respective circuit legs.

22. The equalizer circuitry defined in claim 21 wherein, in each of the NMOS equalizer stages, the controllably variable capacitor and the further controllably variable resistor are connected in parallel with one another between third and fourth nodes that are respectively in the first and second circuit legs between the source-drain path and the controllably variable current source in the respective circuit leg.

23. The equalizer circuitry defined in claim 22 wherein, in each of the NMOS equalizer stages, a signal to be equalized by that stage is applied in complementary form to gates of the NMOS transistors in that stage, and a signal that has been equalized by that stage is output in complementary form from the first and second nodes.

24. Equalizer circuitry on an integrated circuit (“

IC”

) comprising;

a plurality of differential NMOS equalizer stages connected in series, each of the NMOS equalizer stages being programmable to control one of bandwidth and power consumption of the equalizer circuitry;

a differential PMOS equalizer stage connected in parallel with the NMOS equalizer stage that is first in the series; and

control circuitry for determining whether the PMOS equalizer stage or the NMOS equalizer stage that is first in the series will be used.