Translation of register-combiner state into shader microcode

• US 8,223,150 B2
• Filed: 07/28/2011
• Issued: 07/17/2012
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Cabral, Brian, Migdal, Amy J., Bastos, Rui M., Abdalla, Karim M.
• Primary Examiner(s): Hajnik, Daniel
• Assistant Examiner(s): Prendergast, Roberta D
• Application Number:
  US13/193,524
• Publication Number:
  US 20110279473A1
• Time in Patent Office: 355 Days
• Field of Search: 345/426, 345/543, 345/559, 719/328
• US Class Current: 345/426
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/50 Lighting effects
• CPC Class Codes: G06T 2210/32 Image data format

Abstract

An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.

Claims

1. A method for generating shader program instructions to control a fragment shader within a programmable graphics processing pipeline, the method comprising:

receiving, at a combiner instruction processing unit, a fixed function state that represents one or more combiner operations, wherein, to generate the fixed function state, a fixed function application programming interface (API) call to perform the one or more combiner operations on pixel data is converted into one or more state bundles that include the fixed function state;

translating the fixed function state into at least one shader program instruction that, when executed by a fragment shader within the programmable graphics processing pipeline, performs the one or more combiner operations; and

after translating the fixed function state into at least one shader program instruction, providing the at least one shader program instruction to the fragment shader within the programmable graphics processing pipeline for execution.

2. The method of claim 1, further comprising:

determining a number of registers needed to perform the one or more combiner operations based on the fixed function state; and

allocating the number of registers prior to the translating of the fixed function state.

3. The method of claim 2, further comprising remapping the number of registers to pack the registers and produce a register remap table.

4. The method of claim 1, further comprising allocating registers for processing the at least one shader program instruction.

5. The method of claim 4, further comprising remapping the registers to produce a register remap table.

6. The method of claim 1, further comprising determining that a pixel packet to be processed by the fragment shader is a first pixel packet received after a fixed function state change.

7. The method of claim 6, further comprising blocking incoming pixel packets until the fragment shader becomes idle.

8. The method of claim 7, further comprising:

determining that the fragment shader is idle; and

accepting incoming pixel packets to process the incoming pixel packets based on the fixed function state change.

9. The method of claim 1, wherein the fixed function API call comprises a combiner API call, and the one or more fixed function state bundles comprise a combiner state bundle.

10. A method as in claim 1, further comprising executing within the fragment shader the at least one shader program instruction for performing the one or more combiner operations.

11. A system configured to generate shader program instructions to control a fragment shader within a programmable graphics processing pipeline, the system comprising:

a combiner instruction processing unit configured to;

receive a fixed function state that represents one or more combiner operations, wherein, to generate the fixed function state, a fixed function application programming interface (API) call to perform the one or more combiner operations on pixel data is converted into one or more state bundles that include the fixed function state;

translate the fixed function state into at least one shader program instruction that, when executed by a fragment shader within the programmable graphics processing pipeline, performs the one or more combiner operations; and

provide the at least one shader program instruction to the fragment shader within the programmable graphics processing pipeline for execution after translating the fixed function state into at least one shader program instruction.

12. The system of claim 11, further comprising a raster state machine coupled to the combiner instruction processing unit and configured to receive pixel packets and determine whether or not the pixel packets indicate a new fixed function program should be generated by detecting that a pixel packet is a first pixel packet received after a fixed function state change.

13. The system of claim 12, wherein the raster state machine is further configured to block incoming pixel packets until the fragment shader becomes idle.

14. The system of claim 13, wherein the raster state machine is further configured to accept incoming pixel packets to process the incoming pixel packets based on the fixed function state change when the fragment shader becomes idle.

15. The system of claim 11, wherein the combiner instruction processing unit is configured to determine and allocate a number of registers needed to perform the one or more combiner operations call based on the fixed function state.

16. The system of claim 15, wherein the combiner instruction processing unit is configured to remap the registers to pack the registers and produce a register remap table.

17. The system of claim 11, wherein the fixed function API call comprises a combiner API call, and the one or more fixed function state bundles comprises a combiner state bundle.

18. A computing device, comprising:

a subsystem configured to generate shader program instructions to control a fragment shader within a programmable graphics processing pipeline, the subsystem including a combiner instruction processing unit that is configured to;

receive a fixed function state that represents one or more combiner operations, wherein, to generate the fixed function state, a fixed function application programming interface (API) call to perform the one or more combiner operations on pixel data is converted into one or more state bundles that include the fixed function state;

translate the fixed function state into at least one shader program instruction that, when executed by a fragment shader within the programmable graphics processing pipeline, performs the one or more combiner operations; and

provide the at least one shader program instruction to the fragment shader within the programmable graphics processing pipeline for execution after translating the fixed function state into at least one shader program instruction.

19. The computing device of claim 18, wherein the combiner instruction processing unit is configured to determine and allocate a number of registers needed to perform the one or more combiner operations call based on the fixed function state.

20. The computing device of claim 18, wherein the fixed function API call comprises a combiner API call, and the one or more fixed function state bundles comprises a combiner state bundle.