Semiconductor device having memory array, method of writing, and systems associated therewith
First Claim
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1. A semiconductor device, comprising:
- a non-volatile memory cell array;
a control unit configured to generate a mode signal indicating if a flash mode has been enabled;
a write circuit configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received; and
a read circuit configured to read data from the non-volatile memory cell array; and
whereinthe control unit is configured to control the read circuit to read data associated with an address input for a write operation during a pre-read operation; and
the write circuit is configured to disable writing data in memory locations of the non-volatile memory cell array storing data matching the write data during the pre-read operation based on the read data.
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Abstract
In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.
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Citations
15 Claims
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1. A semiconductor device, comprising:
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a non-volatile memory cell array; a control unit configured to generate a mode signal indicating if a flash mode has been enabled; a write circuit configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received; and a read circuit configured to read data from the non-volatile memory cell array; and
whereinthe control unit is configured to control the read circuit to read data associated with an address input for a write operation during a pre-read operation; and the write circuit is configured to disable writing data in memory locations of the non-volatile memory cell array storing data matching the write data during the pre-read operation based on the read data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor device comprising:
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a non-volatile memory cell array; a control unit configured to generate a mode signal indicating if a flash mode has been enabled, the control unit is configured to generate an erase enable signal indicating whether an erase operation is enabled, the control unit configured to generate an erase enable signal indicating the erase operation is not enabled if the mode signal indicating that the flash mode has not been enabled; a write circuit configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received, the write circuit configured to write in the non-volatile memory cell array based on the mode signal and the erase enable signal; and an input buffer configured to output to the write circuit one of input data and erase data based on the erase enable signal, wherein the write circuit includes, a selector configured to selectively output one of a fixed enable signal and an inverse of the input data as a write enable signal based on the mode signal and the erase enable signal, and a write driver configured to write the output from the input buffer in the non-volatile memory cell array if enabled by the write enable signal, the fixed enable signal enabling the write driver if output as the write enable signal. - View Dependent Claims (13, 14, 15)
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Specification