Raising programming currents of magnetic tunnel junctions using word line overdrive and high-k metal gate

• US 8,223,534 B2
• Filed: 01/14/2010
• Issued: 07/17/2012
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chung, Shine, Chung, Tao-Wen, Lin, Chun-Jung, Wang, Yu-Jen, Wang, Hung-Sen
• Primary Examiner(s): Le, Vu
• Application Number:
  US12/687,747
• Publication Number:
  US 20100254181A1
• Time in Patent Office: 915 Days
• Field of Search: 365/158, 365/171, 365/230.06, 365/189.09
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

Claims

1. A method of operating magneto-resistive random access memory (MRAM) cells, the method comprising:

providing an MRAM cell comprising;

a magnetic tunneling junction (MTJ) device; and

a selector comprising a source-drain path serially coupled to the MTJ device;

applying an overdrive voltage to a gate of the selector to turn on the selector; and

supplying a positive power supply voltage to a logic circuit in a same chip as the MRAM cell, wherein the overdrive voltage is higher than the positive power supply voltage.

2. The method of claim 1, wherein the overdrive voltage is higher than the positive power supply voltage by greater than about 2.5 volts.

3. The method of claim 1, wherein the overdrive voltage is higher than the positive power supply voltage by greater than about 110 percent.

4. The method of claim 1, wherein the selector has substantially a same gate structure as a logic metal-oxide-semiconductor (MOS) device in the logic circuit.

5. The method of claim 1, wherein the gate of the selector comprises a gate dielectric having a k value greater than about 7.0, and a metal gate electrode over the gate dielectric.

6. The method of claim 1, wherein the overdrive voltage is applied in the form of a pulse, and wherein the method further comprises, during a period the overdrive voltage is applied, applying a current to write the MTJ device.

7. The method of claim 6, wherein the MRAM cell comprises a first end coupled to a bit-line, and a second end coupled to a source line, and wherein the step of applying the current comprises applying a high voltage and a low voltage to the bit-line and the source line, respectively.

8. The method of claim 7, wherein the high voltage is equal to the overdrive voltage.

9. The method of claim 7, wherein the high voltage is lower than the overdrive voltage.

10. A method of operating a magneto-resistive random access memory (MRAM) array, the method comprising:

providing a semiconductor chip comprising the MRAM array and a logic circuit, wherein the MRAM array comprises;

a plurality of MRAM cells arranged as rows and columns, wherein each of the plurality of MRAM cells comprises;

a magnetic tunneling junction (MTJ) device; and

a selector comprising a source-drain path serially coupled to the MTJ device;

a plurality of bit-lines parallel to each other and extending in a column direction;

a plurality of source lines parallel to each other and extending in a row direction, wherein each of the plurality of MRAM cells is coupled between one of the plurality of bit-lines and one of the plurality of source lines; and

a plurality of word-lines parallel to each other and extending in the row direction, wherein gates of the selectors of the plurality of MRAM cells in a same row are connected to a same one of the plurality of word-lines;

providing a logic power supply voltage to operate the logic circuit;

providing a pulse to one of the plurality of word-lines connected to a selected one of the plurality of MRAM cells to write the selected one of the plurality of MRAM cells, wherein the pulse has an overdrive voltage higher than the logic power supply voltage; and

during a period the overdrive voltage is applied, applying a current flowing through the MTJ device of the selected one of the plurality of MRAM cells.

11. The method of claim 10, wherein the overdrive voltage is higher than the logic power supply voltage by greater than about 2.5 volts.

12. The method of claim 10, wherein the overdrive voltage is higher than the logic power supply voltage by greater than about 110 percent.

13. The method of claim 10, wherein the step of providing the semiconductor chip comprises simultaneously forming the selector and a logic MOS device in the logic circuit, and wherein the logic MOS device is operated by the logic power supply voltage.

14. The method of claim 10, wherein the selector comprises a MOS device comprising a gate dielectric having a k value greater than about 7.0, and a metal gate electrode over the gate dielectric.

15. The method of claim 10 further comprising, during the period, applying a high voltage and a low voltage, respectively, to one of the plurality of bit-lines connected to the selected one of the plurality of MRAM cells and one of the plurality of source lines connected to the selected one of the plurality of MRAM cells.

16. The method of claim 15, wherein the high voltage is equal to the overdrive voltage.

17. The method of claim 15, wherein the high voltage is lower than the overdrive voltage.

18. A method of operating magneto-resistive random access memory (MRAM) cells, the method comprising:

providing an MRAM cell comprising a first end coupled to a bit-line, and a second end coupled to a source line, wherein the MRAM cell comprises;

a magnetic tunneling junction (MTJ) device; and

a selector comprising a source-drain path serially coupled to the MTJ device;

applying an overdrive voltage to a gate of the selector to turn on the selector, wherein the overdrive voltage is applied in the form of a pulse; and

during a period the overdrive voltage is applied, applying a current to write the MTJ device, wherein the step of applying the current comprises applying a high voltage and a low voltage to the bit-line and the source line, respectively.

19. The method of claim 18, wherein the high voltage is equal to the overdrive voltage.

20. The method of claim 18, wherein the high voltage is lower than the overdrive voltage.