Memory system, program method thereof, and computing system including the same

• US 8,223,544 B2
• Filed: 08/29/2011
• Issued: 07/17/2012
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Jun-Ho, Choi, In-Hwan, Chung, Woon-Jae, Yoon, Song-Ho, Ye, Kyung-Wook
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): Tran, Anthan
• Application Number:
  US13/220,194
• Publication Number:
  US 20110314207A1
• Time in Patent Office: 323 Days
• Field of Search: 365/185.03
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device.

Claims

1. A memory system comprising:

a multi-bit flash memory device including a plurality of memory blocks; and

a memory controller configured to control the multi-bit flash memory device,

wherein the memory controller is configured to determine whether there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed in the multi-bit flash memory device; and

when it is determined that there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed in the multi-bit flash memory device, the memory controller is configured to control the multi-bit flash memory device to backup the lower data belonging to a page offset value to a free memory block from the memory blocks.

2. The memory system of claim 1, wherein the memory controller is configured to control the multi-bit flash memory device so that the data to be programmed is programmed in the selected memory block when there exists no lower data belonging to a page offset value on the basis of a start address of data to be programmed.

3. The memory system of claim 1, wherein each of the memory cells is configured to store 2-bit data.

4. The memory system of claim 3, wherein the lower data to be backed up to the backup memory block is LSB data.

5. The memory system of claim 1, wherein each of the memory cells is configured to store M-bit data, where M is an integer of 3 or more.

6. The memory system of claim 5, wherein the lower data to be backed up to the backup memory block is a data bit selected from a group comprising a first data bit to a (M−

1)th data bit.

7. The memory system of claim 1, wherein the memory system is configured to detect whether a power failure occurs with respect to the selected memory block.

8. The memory system of claim 7, wherein the memory controller is configured to control the multi-bit flash memory device so that data backed up to the backup memory block and valid data of the selected memory block are copied to a free memory block when a power failure to the selected memory block is detected.

9. The memory system of claim 1, wherein the multi-bit flash memory device is a NAND flash memory device.

10. The memory system of claim 1, wherein the multi-bit flash memory device and the memory controller constitute an OneNAND™

flash memory device.