Semiconductor memory device adopting improved local input/output line precharging scheme
First Claim
1. A read data path circuit of a semiconductor memory device, the circuit comprising:
- a first sense amplifier; and
a precharging unit including a first conductive type precharging unit, a second conductive type precharging unit, a delay unit, a NAND gate, and an equalizing unit,the first conductive type precharging unit configured to precharge input/output lines that correspond with a second sense amplifier,the equalizing unit configured to equalize a voltage of the input/output lines of the circuit,the second conductive type precharging unit configured to precharge the input/output lines following an elapsed time after the first sense amplifier is activated and while a column selection unit is deactivated, the column selecting unit configured to operationally connect bit lines corresponding with the first sense amplifier to the input/output lines in response to a selection signal,the delay unit configured to delay an enable signal to the second sense amplifier, andthe NAND gate performing a NAND operation on an output of the delay unit and an equalization enable signal of the equalizing unit, to produce a NAND response in order to activate the second conductive type precharging unit.
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Accused Products
Abstract
A semiconductor memory device capable of preventing or minimizing bit line disturbance and performing a low-voltage high-speed operation includes a read data path circuit including a bit line sense amplifier, a local input/output line sense amplifier, a column selecting unit to operationally connect bit lines connected to the bit line sense amplifier to local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal, and a local input/output line precharging unit to precharge the pair of local input/output lines by a first precharging unit, equalizing the pair of local input/output lines by an equalizing unit, and to precharge the local input/output lines by a second precharging unit following an elapsed time after the bit line sense amplifier is activated, while the column selection is deactivated.
389 Citations
16 Claims
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1. A read data path circuit of a semiconductor memory device, the circuit comprising:
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a first sense amplifier; and a precharging unit including a first conductive type precharging unit, a second conductive type precharging unit, a delay unit, a NAND gate, and an equalizing unit, the first conductive type precharging unit configured to precharge input/output lines that correspond with a second sense amplifier, the equalizing unit configured to equalize a voltage of the input/output lines of the circuit, the second conductive type precharging unit configured to precharge the input/output lines following an elapsed time after the first sense amplifier is activated and while a column selection unit is deactivated, the column selecting unit configured to operationally connect bit lines corresponding with the first sense amplifier to the input/output lines in response to a selection signal, the delay unit configured to delay an enable signal to the second sense amplifier, and the NAND gate performing a NAND operation on an output of the delay unit and an equalization enable signal of the equalizing unit, to produce a NAND response in order to activate the second conductive type precharging unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory device comprising:
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a memory cell array including a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including at least one access transistor and one storage capacitor; a plurality of first sense amplifiers electrically connected to corresponding bit lines electrically connected to the plurality of memory cells; a plurality of precharging units each of which includes a first conductive type precharging unit, a second conductive type precharging unit, an equalizing unit, a delay unit and a NAND gate, the first conductive type precharging unit configured to precharge first input/output lines, the equalizing unit configured to equalize a voltage of the first input/output lines, the second conductive type precharging unit configured to precharge the first input/output lines following an elapsed time after an associated first sense amplifier of the plurality of first sense amplifiers is activated and while an associated column selecting unit of a plurality of column selecting units is deactivated, the delay unit configured to delay an enable signal to a corresponding sense amplifier of a plurality of second sense amplifiers, the NAND gate performing a NAND operation on an output of the delay unit and an equalization enable signal of the equalizing unit, to produce a NAND response in order to activate the second conductive type precharging unit. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A read data path circuit of a semiconductor memory device, the circuit comprising:
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a first sense amplifier; a second sense amplifier; a column selecting unit configured to operationally connect bit lines corresponding to the first sense amplifier to input/output lines corresponding to the second sense amplifier, in response to a selection signal; a precharging unit configured to precharge the input/output lines by NMOS transistors, the precharging unit configured to equalize a voltage of the input/output lines by a PMOS transistor, and the precharging unit configured to precharge the input/output lines by PMOS transistors following an elapsed time after the first sense amplifier is activated and the selection signal is deactivated, the precharging unit including a delay unit configured to delay an enable signal to the second sense amplifier; and a NAND gate performing a NAND operation on an output of the delay unit and an equalization enable signal of the PMOS transistor for equalizing, to produce a NAND response in order to activate the second conductive type precharging unit. - View Dependent Claims (16)
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Specification