Application-specific integrated circuit for monitoring and optimizing interlayer network performance

• US 8,223,654 B2
• Filed: 05/31/2007
• Issued: 07/17/2012
• Est. Priority Date: 08/22/2006
• Status: Active Grant

• Current Assignee: CenturyLink Intellectual Property LLC (Lumen Technologies, Inc.)
• Original Assignee: Embarq Holdings Company LLC (Lumen Technologies, Inc.)
• Inventors: Bugenhagen, Michael K.
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): MENSAH, PRINCE AKWASI
• Application Number:
  US11/809,883
• Publication Number:
  US 20080049769A1
• Time in Patent Office: 1,874 Days
• Field of Search: 370/352, 370/356, 370/401, 370/392, 370241-253, 709223-226
• US Class Current: 370/241
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications
• CPC Class Codes: H04L 41/147 for predicting network behaviour
• CPC Class Codes: H04L 41/149 for prediction of maintenance
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 41/5003 Managing SLA; Interaction between SLA and QoS
• CPC Class Codes: H04L 41/5009 Determining service level performance parameters or violations of service level contracts, e.g. violations of agreed response time or mean time between failures [MTBF]
• CPC Class Codes: H04L 43/0829 Packet loss
• CPC Class Codes: H04L 43/0852 Delays
• CPC Class Codes: H04L 43/087 Jitter
• CPC Class Codes: H04L 43/0882 Utilisation of link capacity
• CPC Class Codes: H04L 43/16 Threshold monitoring

Abstract

An application-specific integrated circuit for use in optimizing a packet network including a processing unit that processes defined sequences of assembler language and executes defined sequences of assembler instructions; program and data memory that stores the defined sequences of assembler instructions; an internal data bus; and an input/output (I/O) interface arranged between the internal data bus and at least one external network device for communicating data packets containing network performance information between the internal data bus and the at least one external network device.

Claims

1. An application-specific integrated circuit for use in optimizing a packet network, the application-specific integrated circuit comprising:

a processing unit that executes instructions;

a memory that stores said instructions;

an internal data bus;

an input/output (I/O) interface arranged between said internal data bus and at least one external network device for communicating data packets containing network performance information between said internal data bus and said at least one external network device;

a first data path line in communication with said processing unit designated for communicating only packets that include real-time data content, wherein the first data path line in communication with said processing unit is coupled to a first network interface port that is designated for receiving only packets that include real-time data content;

a second data path line in communication with said processing unit designated for communicating only packets that do not include real-time data content, wherein the second data path line in communication with said processing unit is coupled to a second network interface port that is designated for receiving only packets that do not include real-time data content;

a third data path line in communication with said processing unit designated for communicating only packets that include real-time data content, wherein the a third data path line in communication with said processing unit is coupled to a third network interface port that is designated for transmitting only packets that include real-time data content; and

a fourth data path line in communication with said processing unit designated for communicating only packets that do not include real-time data content, wherein the fourth data path line in communication with said processing unit is coupled to a fourth network interface port that is designated for transmitting only packets that do not include real-time data content.

2. The application-specific integrated circuit for use in optimizing a packet network of claim 1 wherein said I/O interface is capable of communicating with one of network interfaces, single or multiple, such as T1 interfaces, E1 interfaces, Integrated Services Digital Network (ISDN) interfaces, SS7 interfaces, Optical Carrier level-3 (OC-3) interfaces, other optical interfaces, any other types of interfaces, or combinations of these interfaces.

3. The application-specific integrated circuit for use in optimizing a packet network of claim 1 is configured to:

create sampling shift registers with one of quality of service and mapping/replication services.

4. The application-specific integrated circuit for use in optimizing a packet network of claim 1 a static register configured to:

allocate at least one of total volume of real-time data content and total volume of non-real-time data content based on at least one of per data packet stream, per total data flow, per logical connection, per I/O port, and per network element.

5. The application-specific integrated circuit for use in optimizing a packet network of claim 1 wherein said application-specific integrated circuit is configured to:

schedule modification to provide actual scheduler performance information on what flows are being served at what rates.

6. The application-specific integrated circuit for use in optimizing a packet network of claim 1 wherein said application-specific integrated circuit is configured to:

count each of said data packets that includes at least one of TOS or QoS markings.

7. The application-specific integrated circuit for use in optimizing a packet network of claim 1 wherein said data packets are IEEE standard 802.1AG data packets.

8. The application-specific integrated circuit for use in optimizing a packet network of claim 1 wherein said application-specific integrated circuit is configured to:

recognize data packets containing real-time data and data packets containing non-real-time data based on the port or network device that is transmitting the data packets to said application-specific integrated circuit.

9. The application-specific integrated circuit for use in optimizing a packet network of claim 1 wherein said application-specific integrated circuit is configured to:

recognize at least one of a payload of said data packets, a p-bit of said data packets, and header information in said data packets.

10. The application-specific integrated circuit for use in optimizing a packet network of claim 1 wherein said application-specific integrated circuit is further configured to:

calculate one of peakedness and burst in real-time.

11. The application-specific integrated circuit for use in optimizing a packet network of claim 1, wherein said application-specific integrated circuit is further configured to:

transmit the at least one of a total volume of real-time data content and a total volume of non-real-time data content to other devices or systems for adjusting said other devices or systems to optimize real-time content flow through a network.