Power amplifier predistortion methods and apparatus using envelope and phase detector

• US 8,224,266 B2
• Filed: 09/02/2008
• Issued: 07/17/2012
• Est. Priority Date: 08/30/2007
• Status: Active Grant

• Current Assignee: Dali Systems Co., Ltd.
• Original Assignee: Dali Systems Co., Ltd.
• Inventors: Liu, Dongtai, Yang, Dali, Anderson, James
• Primary Examiner(s): Chen, Junpeng
• Application Number:
  US12/203,076
• Publication Number:
  US 20090096521A1
• Time in Patent Office: 1,414 Days
• Field of Search: 455/114.3, 455/91, 455/67.11, 455/67.13, 455/127.1, 455/126, 330/149, 375/295, 375/296, 375/297
• US Class Current: 455/114.3
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 1/3294 Acting on the real and imaginary components of the input signal
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/192 A hybrid coupler being used at the input of an amplifier circuit
• CPC Class Codes: H03F 2200/204 A hybrid coupler being used at the output of an amplifier circuit
• CPC Class Codes: H03F 2200/321 Use of a microprocessor in an amplifier circuit or its control circuit
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion

Abstract

An embodiment of the invention is a predistortion approach to linearize a power amplifier without frequency conversion of the RF signals by using envelope and phase detectors to detect the error to be corrected, and then one or more analog multiplier(s) and a DSP-based processor. For the analog embodiment, the inherent nature of the analog circuitries allows digital predistortion processing structured directly at the RF band, and enables a single power amplifier to support multi-modulation schemes, multi-carriers and multi-channels. As a result, the predistortion architecture is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems. The wireless system performance can be improved and upgraded just by using the new PA module rather than change or rebuild new subsystem in existing base station. The analog embodiment can also mix and match its analog multipliers with other analog components such as phase splitters, phase shifters, attenuators, filters, couplers, mixers, low-noise amplifiers, buffers, envelope detectors, and etc., to provide additional features.

Claims

1. A predistortion architecture for use with power amplifiers for wireless communications systems, the predistortion architecture comprising:

an input for receiving signals representative of RF band signals,

a first envelope detector responsive to representative signals of RF band input signals at an input of a modulator for providing a first input to a time-division multiplexer;

a second envelope detector adapted to be responsive to an output signal representative of the output signals of a power amplifier for providing a second input to the time-division multiplexer;

a phase detector responsive to the signals representative of the RF band input signals and the signals representative of the power amplifier output signals for providing a third input to the time-divisional multiplexer;

a digital predistortion processor responsive to inputs from the time-division multiplexer for generating predistortion correction signals as an output; and

logic for converting the output of the digital predistortion processor into analog predistortion correction signals and combining them with the RF input signals.

2. The predistortion architecture of claim 1 wherein the time-divisional multiplexer comprises a 3:

1 multiplexer.

3. The predistortion architecture of claim 1 wherein the digital predistortion processor comprises a lookup table.

4. The predistortion architecture of claim 3 wherein the lookup table is characterized by a polar format.

5. The predistortion architecture of claim 1 wherein the logic comprises a plurality of digital to analog converters, a plurality of multipliers, and an adder.

6. The predistortion architecture of claim 1 further comprising an analog to digital converter coupled between the time-division multiplexer and the digital predistortion processor.

7. A system for predistorting power amplifiers, the system comprising:

a power amplifier;

a plurality of Radio Frequency (RF) couplers for sampling an RF input and an RF output signal;

a voltage dependent phase shifter communicatively coupled to a voltage dependent amplitude adjuster, the amplitude adjuster configured to provide an input to the power amplifier;

a plurality of Radio Frequency (RF) envelope detectors, each communicatively coupled to at least one of the plurality of RF couplers, at least one envelope detector configured to receive signals representative of the RF input signal, and at least one envelope detector configured to receive signals representative of output signals from the power amplifier;

a Radio Frequency (RF) phase detector communicatively coupled to at least one of the plurality of RF couplers, and configured to receive signals representative of the RF input signal and determine a phase error signal based on the RF input signal;

a time division multiplexer communicatively coupled to the phase detector and at least one of the plurality of envelope detectors;

a digital predistortion processor with A/D and D/A converters, at least one of the D/A converters being communicatively coupled to the phase shifter or amplitude adjuster and at least one of the A/D converters being communicatively coupled to the time division multiplexer; and

a look up table communicatively coupled to the digital predistortion processor, for compensating an amplitude and phase distortion.

8. The system of claim 7 further comprising a time delay incorporated in the phase shifter.

9. The system of claim 7 wherein the time-divisional multiplexer comprises a 3:

1 multiplexer.

10. The system of claim 7 wherein the digital predistortion processor comprises a lookup table.

11. The system of claim 10 wherein the lookup table is characterized by a polar format.

12. A system for predistorting power amplifiers, the system comprising:

a power amplifier;

a plurality of Radio Frequency (RF) couplers for sampling an RF input and an RF output signal;

a phase shifter communicatively coupled to at least one of a plurality of voltage dependent amplitude adjusters, at least one of the amplitude adjusters configured to provide an input to the power amplifier;

a plurality of Radio Frequency (RF) envelope detectors, each communicatively coupled to at least one of the plurality of RF couplers, at least one envelope detector configured to receive signals representative of the RF input signal, and at least one envelope detector configured to receive signals representative of output signals from the power amplifier;

a Radio Frequency (RF) phase detector communicatively coupled to at least one of the plurality of RF couplers, and configured to receive signals representative of the RF input signal and determine a phase error signal based on the RF input signal;

a time division multiplexer communicatively coupled to the phase detector and at least one of the plurality of envelope detectors;

a digital predistortion processor with A/D and D/A converters, at least one of the D/A converters being communicatively coupled to the phase shifter or one of the plurality of amplitude adjusters and at least one of the A/D converters being communicatively coupled to the time division multiplexer; and

a look up table communicatively coupled to the digital predistortion processor, for compensating an amplitude and phase distortion.

13. The system of claim 12 wherein the phase shifter includes a time delay element.

14. The system of claim 12 wherein the time-divisional multiplexer comprises a 3:

1 multiplexer.

15. The system of claim 12 wherein the digital predistortion processor comprises a lookup table.

16. The system of claim 15 wherein the lookup table is characterized by a polar format.