Use of a first two-wire interface communication to support the construction of a second two-wire interface communication

• US 8,225,024 B2
• Filed: 03/07/2005
• Issued: 07/17/2012
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Dybsetter, Gerald L.
• Primary Examiner(s): SNYDER, STEVEN G
• Application Number:
  US11/074,608
• Publication Number:
  US 20050237991A1
• Time in Patent Office: 2,689 Days
• Field of Search: 710/11, 370/349
• US Class Current: 710/315
• CPC Class Codes: H04L 25/00 Baseband systems

Abstract

A telecommunications system and constituent two-wire interface module. The two-wire interface module includes a first two-wire interface component configured to receive a first two-wire interface communication following a first two-wire interface protocol, and a second two-wire interface component configured to generate a second two-wire interface communication following a second two-wire interface protocol. The first and second two-wire interface communications each include a header portion and a payload portion. The second two-wire interface component is further configured to use one or more of the data fields from the payload portion of the first two-wire interface communication in the header portion of the second two-wire interface communication.

Claims

1. A two-wire interface module comprising the following:

a first two-wire interface component configured to receive a first two-wire interface communication following a first two-wire interface protocol, the first two-wire interface communication including a header portion and a payload portion, the payload portion including a plurality of data fields;

a logic component configured to extract one or more of the plurality of data fields from the payload portion of the first two-wire interface communication; and

a second two-wire interface component configured to generate a second two-wire interface communication following a second two-wire interface protocol, the second two wire interface communication including a header portion and a payload portion, wherein the second two-wire interface component is further configured to receive the one or more of the plurality of data fields extracted from the payload portion from the logic component and to insert the one or more of the plurality of data fields extracted from the payload portion in the header portion of the second two-wire interface communication;

wherein the second two-wire interface protocol comprises a Finisar Serial Bus (FSB) two-wire interface protocol and communications following the FSB two-wire interface protocol include;

a preamble field;

a frame start field;

an operation field;

a device identifier field;

a basic address field;

a first bus turnaround field;

a data field;

a second bus turnaround field; and

a frame end field.

2. A two-wire interface module in accordance with claim 1, wherein the first two-wire interface protocol comprises an Inter-Integrated Circuit (I²C) two-wire interface.

3. A two-wire interface module in accordance with claim 1, wherein the extracted one or more of the plurality of data fields comprises a frame start field.

4. A two-wire interface module in accordance with claim 1, wherein the extracted one or more of the plurality of data fields comprises an operation field and wherein bits in the operation field determine a frame structure of the second two-wire interface communication.

5. A two-wire interface module in accordance with claim 1, wherein the extracted one or more of the plurality of data fields comprises a device identifier field.

6. A two-wire interface module in accordance with claim 1, wherein the extracted one or more of the plurality of data fields comprises an address field.

7. A two-wire interface module in accordance with claim 1, wherein the extracted one or more of the plurality of data fields comprises security information that improves reliability of the second two-wire interface communication.

8. A two-wire interface module in accordance with claim 7, wherein the extracted one or more of the plurality of data fields comprises a Cyclic Redundancy Checking (CRC) field.

9. A two-wire interface module in accordance with claim 1, wherein the extracted one or more of the plurality of data fields comprises a frame end field.

23. A two-wire interface module in accordance with claim 1, wherein the two-wire interface module is selectively configurable to operate in an active mode and in an inactive mode, the active mode using the logic component and second two-wire interface component to convert the first two-wire interface communication into the second two-wire interface communication and the inactive mode allowing the first two-wire interface communication to pass through without conversion by the logic component and the second two-wire interface component.

24. The two-wire interface module of claim 1, wherein communications following the FSB two-wire interface protocol further include:

an extended field;

a bus hold field;

a cyclic redundancy checking field;

an acknowledgement field; and

an error status field.

27. The two-wire interface module of claim 1, wherein:

the first two-wire interface component comprises a first interface wire, a second interface wire, and a configuration input;

the logic component is configured to communicate over the first and second two-wire interface wires using the first two-wire interface protocol when the configuration input receives a first input signal correlating to the first two-wire interface protocol; and

the logic component is configured to communicate over the first and second two-wire interface wires using the second two-wire interface protocol when the configuration input receives a second input signal correlating to the second two-wire interface protocol.

10. A telecommunications system comprising a two-wire interface module, the two-wire interface module comprising the following:

a first two-wire interface component configured to receive a first two-wire interface communication following a first two-wire interface protocol, the first two-wire interface communication including a header portion and a payload portion, the payload portion including a plurality of data fields; and

a second two-wire interface component configured to generate a second two-wire interface communication following a second two-wire interface protocol, the second two-wire interface communication including a header portion and a payload portion, wherein the second two-wire interface component is further configured to use one or more of the plurality of data fields from the payload portion of the first two-wire interface communication in the header portion of the second two-wire interface communication,

wherein the second two-wire interface communication includes a preamble field having a series of “

n”

consecutive bits of the same polarity and includes bits interspersed in the communication at a guaranteed minimum frequency that is at least every “

n”

bits, the interspersed bits having a polarity opposite that of the consecutive preamble bits to prevent non-preamble portions of the second two-wire interface communication from being mistakenly interpreted as a preamble, wherein “

n”

is an integer greater than or equal to 2;

wherein communications following the second two-wire interface protocol include;

a preamble field;

a frame start field;

an operation field;

a device identifier field;

a basic address field;

a first bus turnaround field;

a data field;

a second bus turnaround field; and

a frame end field.

11. A telecommunications system in accordance with claim 10, wherein the second two-wire interface component is an external memory.

12. A telecommunications system in accordance with claim 11, further comprising the following:

a third two-wire interface component configured to receive the second two-wire interface communication.

13. A telecommunications system in accordance with claim 10, further comprising the following:

a third two-wire interface component configured to receive the second two-wire interface communication.

14. A telecommunications system in accordance with claim 10, wherein the first two-wire interface protocol comprises an Inter-Integrated Circuit (I²C) two-wire interface.

15. A telecommunications system in accordance with claim 14, wherein the second two-wire interface protocol comprises a Finisar Serial Bus (FSB) two-wire interface.

16. A telecommunications system in accordance with claim 10, wherein the second two-wire interface protocol comprises a Finisar Serial Bus (FSB) two-wire interface.

17. A telecommunications system in accordance with claim 10, wherein the telecommunications system is one of a 1 G laser transceiver, a 2.5 G laser transceiver, a 4 G laser transceiver, a 10 G laser transceiver, or a laser transceiver suitable for fiber channels greater than 10 G.

18. A telecommunications system in accordance with claim 10, wherein the telecommunications system is a 10 Gigabit Small Form Factor Pluggable (XFP) laser transceiver.

19. A telecommunications system in accordance with claim 10, wherein the telecommunications system is a Small Form Factor Pluggable (SFP) laser transceiver.

20. A telecommunications system in accordance with claim 10, wherein the telecommunications system is a Small Form Factor (SFF) laser transceiver.

22. A telecommunications system in accordance with claim 10, wherein the preamble includes a predetermined number of consecutive same polarity bits, and wherein the bits interspersed at the guaranteed minimum frequency are guaranteed to be spaced apart from each other by less than the predetermined number of preamble bits.

25. The telecommunications system of claim 10, wherein communications following the second two-wire interface protocol further include:

an extended field;

a bus hold field;

a cyclic redundancy checking field;

an acknowledgement field; and

an error status field.

28. The telecommunications system of claim 10, further comprising a logic component, wherein:

the first two-wire interface component comprises a first interface wire, a second interface wire, and a configuration input;

the logic component is configured to communicate over the first and second two-wire interface wires using the first two-wire interface protocol when the configuration input receives a first input signal correlating to the first two-wire interface protocol; and

the logic component is configured to communicate over the first and second two-wire interface wires using the second two-wire interface protocol when the configuration input receives a second input signal correlating to the second two-wire interface protocol.

21. An optical transceiver comprising:

a two-wire interface module configured to load optical transceiver instructions from a memory module external to the optical transceiver into a register internal to the optical transceiver, the two-wire interface module comprising;

a first two-wire interface component configured to receive a first two-wire interface communication from the memory module, the first two-wire interface communication including a header portion and at least one of the optical transceiver instructions in a payload portion thereof; and

a second two-wire interface component configured to transmit a second two-wire interface communication to the register, the second two-wire interface communication including a header portion and the least one of the optical transceiver instructions in a payload portion thereof, the second two-wire interface component being further configured to transplant one or more of a plurality of data fields from the payload portion of the first two-wire interface communication into the header portion of the second two-wire interface communication,

the first two-wire interface communication conforming with a non-guaranteed header two-wire interface protocol in which the payload portion includes a plurality of words and the header portion identifies an operation corresponding to each of the plurality of words, and

the second two-wire interface communication conforming with a guaranteed header two-wire interface protocol in which the payload portion is a single word and the header portion identifies an operation corresponding to the single word; and

an optical transceiver component configured to operate based on the optical transceiver instructions loaded into the register;

wherein communications following the second two-wire interface protocol include;

a preamble field;

a frame start field;

an operation field;

a device identifier field;

a basic address field;

a first bus turnaround field;

a data field;

a second bus turnaround field; and

a frame end field.

26. The optical transceiver of claim 21, wherein communications following the second two-wire interface protocol further include:

an extended field;

a bus hold field;

a cyclic redundancy checking field;

an acknowledgement field; and

an error status field.

29. The optical transceiver of claim 21, further comprising a logic component, wherein:

the first two-wire interface component comprises a first interface wire, a second interface wire, and a configuration input;

the logic component is configured to communicate over the first and second two-wire interface wires using the first two-wire interface protocol when the configuration input receives a first input signal correlating to the first two-wire interface protocol; and

the logic component is configured to communicate over the first and second two-wire interface wires using the second two-wire interface protocol when the configuration input receives a second input signal correlating to the second two-wire interface protocol.