Lateral cache-to-cache cast-in

• US 8,225,045 B2
• Filed: 12/16/2008
• Issued: 07/17/2012
• Est. Priority Date: 12/16/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guthrie, Guy L., Ng, Alvan W., Siegel, Michael S., Starke, William J., Williams, Derek E., Williams, Phillip G.
• Primary Examiner(s): Savla, Arpan P.
• Application Number:
  US12/335,975
• Publication Number:
  US 20100153647A1
• Time in Patent Office: 1,309 Days
• Field of Search: 711/122, 711/133, 711/118, 711/119
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

Claims

1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising:

installing each of a plurality of cache lines in a congruence class of the first lower level cache and recording, in the first lower level cache, an access chronology for the plurality of cache lines and a respective membership of each of the plurality of cache lines in one of a plurality of classes including at least a first class and a second class, wherein recording a respective membership includes recording membership in the first class for one or more cache lines of the congruence class installed in response to a first access by the first processing unit that missed in the first lower level cache and recording a respective membership in the second class for one or more cache lines of the congruence class for which a subsequent second access by the first processing unit resulted in a hit in the first lower level cache;

thereafter, in response to a data request, selecting a victim cache line to be castout from the congruence class in the first lower level cache, wherein the selecting includes selecting the victim cache line from among one or more cache lines in the second class while excluding one or more cache lines in the first class from the selection;

the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination of the victim cache line; and

in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache.

2. The method of claim 1, wherein the first and second lower level caches are victim caches.

3. The method of claim 1, wherein:

the victim cache line is a first victim cache line; and

the method further comprises evicting a second victim cache line from the second lower level cache to make room for the first victim cache line in the second lower level cache.

4. The method of claim 1, wherein said lateral castout command identifies the second lower level cache as the destination.

5. The method of claim 1, and further comprising:

in response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit transmitting the victim cache line to the second lower level cache.

6. The method of claim 1, wherein the step of removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache is performed without transmitting the victim cache line from the first lower level cache to the second lower level cache.

7. The method of claim 1, wherein membership of the one or more cache lines in the second class indicates the one or more cache lines in the second class are also held in the first upper level cache.

8. The method of claim 1, wherein the first and second accesses comprise prefetch requests.

9. A data processing system, comprising:

an interconnect fabric; and

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches;

wherein the first lower level cache includes;

the data array including a congruence class, wherein the congruence class includes a plurality of cache lines;

a directory in the first lower level cache that holds an access chronology for the plurality of cache lines in the congruence class and that additionally holds a respective membership of each of the plurality of cache lines in one of a plurality of classes, wherein the plurality of classes includes at least a first class and a second class;

a cache controller that records a respective membership for each of the plurality of cache lines in one of the plurality of classes, wherein the cache controller records membership in the first class for one or more cache lines of the congruence class installed in the congruence class in response to a first access by the first processing unit that missed in the first lower level cache and recording a respective membership in the second class for one or more cache lines of the congruence class for which a subsequent second access by the first processing unit resulted in a hit in the first lower level cache;

wherein the first processing unit, in response to a data request, selects a victim cache line to be castout from the congruence class from among one or more cache lines in the second class while excluding one or more cache lines in the first class from the selection and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache and indicating that a lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache and the second lower level cache holds the victim cache line.

10. The data processing system of claim 9, wherein the first and second lower level caches are victim caches.

11. The data processing system of claim 9, wherein:

the victim cache line is a first victim cache line; and

the second lower level cache evicts a second victim cache line to make room for the first victim cache line in the second lower level cache.

12. The data processing system of claim 9, wherein said lateral castout command identifies the second lower level cache as the destination.

13. The data processing system of claim 9, wherein the first processing unit transmits the victim cache line to the second lower level cache in response to a coherence response to the LCO command indicating success of the LCO command.

14. The data processing system of claim 9, wherein the first processing unit refrains from transmitting the victim cache line to the second lower level cache when removing the victim cache line from the first lower level cache.

15. The data processing system of claim 9, wherein membership of the one or more cache lines in the second class indicates the one or more cache lines in the second class are also held in the first upper level cache.

16. The data processing system of claim 9, wherein the first and second accesses comprise prefetch requests.

17. A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, the processing unit comprising:

the processing unit has a first processor core and associated first upper and first lower level caches;

wherein the first lower level cache includes;

the data array including a congruence class, wherein the congruence class includes a plurality of cache lines;

a directory in the first lower level cache that records an access chronology for the plurality of cache lines in the congruence class and that records a respective membership of each of the plurality of cache lines in one of a plurality of classes, wherein the plurality of classes includes at least a first class and a second class;

a cache controller that records a respective membership for each of the plurality of cache lines in one of the plurality of classes, wherein the cache controller records membership in the first class for one or more cache lines of the congruence class installed in the congruence class in response to a first access by the processing unit that missed in the first lower level cache and recording a respective membership in the second class for one or more cache lines of the congruence class for which a subsequent second access by the processing unit resulted in a hit in the first lower level cache;

wherein the processing unit, in response to a data request, selects a victim cache line to be castout from the congruence class from among one or more cache lines in the second class while excluding one or more cache lines in the first class from the selection and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache and indicating that a lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache for storage in a second lower level cache.

18. The processing unit of claim 17, wherein the first and second lower level caches are victim caches.

19. The processing unit of claim 17, wherein said lateral castout command identifies the second lower level cache as the destination.

20. The processing unit of claim 17, wherein the first processing unit transmits the victim cache line to the second lower level cache in response to a coherence response to the LCO command indicating success of the LCO command.

21. The processing unit of claim 17, wherein the processing unit refrains from transmitting the victim cache line to the second lower level cache when removing the victim cache line from the first lower level cache.

22. The processing unit of claim 17, wherein membership of the one or more cache lines in the second class indicates the one or more cache lines in the second class are also held in the first upper level cache.

23. The processing unit of claim 17, wherein the first and second accesses comprise prefetch requests.