Memory system with pre-fetch operation

• US 8,225,047 B2
• Filed: 02/27/2009
• Issued: 07/17/2012
• Est. Priority Date: 03/01/2008
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yano, Junji, Matsuzaki, Hidenori, Hatsuda, Kosuke
• Primary Examiner(s): SONG, HUA JASMINE
• Application Number:
  US12/394,692
• Publication Number:
  US 20090222629A1
• Time in Patent Office: 1,236 Days
• Field of Search: 711/103, 711/137, 711/201, 711/204, 711/213, 711/E12.001, 711/E12.008, 711/E12.057
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/214 Solid state disk

Abstract

A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing area as a cache memory included in a semiconductor memory and transfers the data to the host apparatus. The controller performs, when a readout request from the host apparatus satisfies a predetermined condition, at least one of first pre-fetch for reading out, to the first storing area data from a terminal end of a logical address range designated by a readout request being currently processed to a boundary of a logical address aligned in the page unit and a second pre-fetch for reading out data from the boundary of the logical address aligned in the page unit to a next boundary of the logical address.

Claims

1. A memory system comprising:

a volatile semiconductor memory;

a nonvolatile semiconductor memory from which data is read out and to which data is written in a page unit and in which data is erased in a block unit, the block unit being twice or larger natural number times as large as the page unit; and

a controller configured to transfer data stored in the nonvolatile semiconductor memory to the volatile semiconductor memory, when the data designated by a readout request is stored in the nonvolatile semiconductor memory, said controller configured to predict the amount of data to be transferred based on at least one prior data transfer and to perform one of a first pre-fetch and a second pre-fetch in dependence upon the predicted amount of data to be transferred, wherein

performing the first pre-fetch includes reading out data, from the nonvolatile semiconductor memory to the volatile semiconductor memory, which corresponds to data between a terminal end of a logical address range designated by a readout request being currently processed and a boundary of a logical address aligned in the page unit in which the terminal end is included; and

performing the second pre-fetch includes reading out data, from the nonvolatile semiconductor memory to the volatile semiconductor memory, which corresponds to data between a terminal end of a logical address range designated by a readout request being currently processed and a next boundary of the logical address aligned in the page unit.

2. The memory system according to claim 1, wherein the nonvolatile semiconductor memory includes:

a first storage area in which data is stored in a first management unit that is smaller than the page unit; and

a second storage area in which data is stored in a second management unit twice or larger natural number times as large as the first management unit and larger than the page unit, and

the controller determines whether all data as the first pre-fetch targets are stored in the second storage area and performs the first pre-fetch when the controller determines that all data as the first pre-fetch targets are stored in the second storage area.

3. The memory system according to claim 1, wherein the nonvolatile semiconductor memory includes:

a first storage area in which data is stored in a first management unit that is smaller than the page unit; and

a second storage area in which data is stored in a second management unit twice or larger natural number times as large as the first management unit and larger than the page unit, and

the controller determines whether all data as the second pre-fetch targets are stored in the second storage area and performs the second pre-fetch when the controller determines that all data as the second pre-fetch targets are stored in the second storage area.

4. The memory system according to claim 1, wherein

the controller performs the first pre-fetch when a terminal end of a logical address range designated by a readout request being currently processed does not correspond to a boundary of the logical address aligned in the page unit.

5. The memory system according to claim 1, wherein

the controller performs the second pre-fetch when a terminal end of a logical address range designated by a readout request being currently processed corresponds to a boundary of the logical address aligned in the page unit.

6. The memory system according to claim 1, wherein the controller performs the second pre-fetch when the controller performs the first pre-fetch.

7. The memory system according to claim 1, wherein

the controller performs the first pre-fetch when the data included in the logical address range designated by a readout request being currently processed is stored in the nonvolatile semiconductor memory.

8. The memory system according to claim 1, wherein

when the controller performs the second pre-fetch, from the nonvolatile semiconductor memory to the volatile semiconductor memory, the controller reads out data that corresponds to a plurality of continuous logical addresses aligned in the page unit.

9. The memory system according to claim 1, wherein the controller performs the second pre-fetch when a first data designated by the readout request being currently processed and a second data designated by immediately preceding the readout request being currently processed have a same transfer size.

10. The memory system according to claim 1, wherein the controller performs the second pre-fetch when a transfer size designated by the readout request being currently processed is within a first size range.

11. The memory system according to claim 9, wherein the controller performs the second pre-fetch when the transfer size is within a first size range.

12. The memory system according to claim 1, wherein the controller performs the second pre-fetch when a first data designated by the readout request being currently processed and a second data designated by immediately preceding the readout request being currently processed are designated continuous logical addresses.

13. The memory system according to claim 9, wherein the controller performs the second pre-fetch when the first data and the second data are designated continuous logical addresses.

14. The memory system according to claim 11, wherein the controller performs the second pre-fetch when the first data and the second data are designated continuous logical addresses.

15. The memory system according to claim 1, wherein the controller performs the second pre-fetch when:

a first data designated by the readout request being currently processed;

a second data designated by immediately preceding the readout request being currently processed;

a third data designated by second immediately preceding the readout request being currently processed have a same transfer size; and

the transfer size is within a second size range and the first data, the second data, and the third data are designated continuous logical addresses.

16. The memory system according to claim 10, wherein the first size range is set based on the access unit frequently used in sequential read and random read from the host apparatus.

17. The memory system according to claim 11, wherein the first size range is set based on the access unit frequently used in sequential read and random read from the host apparatus.

18. The memory system according to claim 15, wherein the second size range is set based on an access unit frequently used in sequential read from the host apparatus.

19. The memory system according to claim 1, wherein the nonvolatile semiconductor memory is a NAND type flash memory.

20. The memory system according to claim 1, wherein the volatile semiconductor memory is a dynamic random access memory (DRAM).