Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements

• US 8,225,073 B2
• Filed: 03/06/2009
• Issued: 07/17/2012
• Est. Priority Date: 11/30/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L., Smith, Stephen J., Watson, John
• Primary Examiner(s): Chan, Eddie P
• Assistant Examiner(s): PARTRIDGE, WILLIAM B
• Application Number:
  US12/399,671
• Publication Number:
  US 20090172137A1
• Time in Patent Office: 1,229 Days
• Field of Search: None
• US Class Current: 712/15
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.

Claims

1. A system for adaptive configuration, the system comprising:

a memory;

a configurable logic computational unit having a first configurable architecture including a first plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components and a configurable logic interconnection network configurably coupling the first plurality of computational elements, the configurable logic interconnection network adapted to configure the first plurality of computational elements for performing a first logic function in response to first logic configuration information stored by the memory, the configurable logic interconnection network further adapted to reconfigure the first plurality of computational elements for performing a second logic function in response to second logic configuration information stored by the memory; and

a configurable digital signal processing computational unit having a second configurable architecture including a second plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous and a digital signal processing interconnection network configurably coupling the second plurality of computational elements together, the digital signal processing interconnection network adapted to configure the second plurality of computational elements for performing a first digital signal processing function in response to first digital signal processing configuration information stored by the memory, the digital signal processing interconnection network further adapted to configure the second plurality of computational elements for performing a second digital signal processing function in response to second digital signal processing configuration information stored by the memory.

2. The system of claim 1, wherein the configurable logic interconnection network includes multiplexers that selectively interconnect the first plurality of computational elements for the first logic function in response to the first logic configuration information and selectively interconnect the first plurality of computational elements for the second logic function in response to the second logic configuration information, and wherein the digital signal processing interconnection network includes multiplexers that selectively interconnect the second plurality of heterogeneous computational elements for the first digital signal processing function in response to the first digital signal processing configuration information and selectively interconnect the second plurality of heterogeneous computational elements for the second digital signal processing function in response to the second digital signal processing configuration information.

3. The system of claim 2, further comprising a configuration network to selectively route the logic configuration information and digital signal processing configuration information to the memory.

4. The system of claim 1, wherein the configurable logic interconnection network is adapted to configure at one point in time the first plurality of computational elements for performing the first logic function in response to the first logic configuration information, and the configurable logic interconnection network is further adapted to reconfigure at another point in time the first plurality of computational elements for performing the second logic function in response to the second logic configuration information.

5. The system of claim 4, wherein the configurable logic unit is further configured to determine a system configuration capacity prior to utilizing the second logic configuration information to reconfigure for the second logic function.

6. The system of claim 1, wherein the first plurality of computational elements of the configurable logic computational unit includes a first type of heterogeneous computational element for performing a first operation and a second type of heterogeneous computational element for performing a second operation.

7. The system of claim 1, wherein the first plurality of computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

8. The system of claim 7, wherein the first plurality of computational elements of the configurable logic computational unit further includes a third type of computational element for performing a third operation from the group of an adder, a register, or a function generator having data inputs and a control input to select a specific function.

9. The system of claim 1, wherein the first logic function is a combinational logic function or a register function, and the second logic function is a combinational logic function or a register function.

10. The system of claim 1, wherein the second plurality of heterogeneous computational elements of the digital signal processing computational unit each perform a different function from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

11. The system of claim 1, wherein a third digital signal processing configuration information is stored by the memory, and wherein the digital signal processing interconnection network is further adapted to configure the second plurality of heterogeneous computational elements to perform another digital signal processing function in response to the third digital signal processing configuration information.

12. The system of claim 11, wherein the other digital signal processing function is one of fixed point arithmetic functions, floating point arithmetic functions, filter functions, and transformation functions.

13. The system of claim 1, wherein at least one of the respective logic and digital signal processing configuration information is transferred to the system from a machine-readable medium.

14. The system of claim 1, wherein the respective logic and digital signal processing configuration information are each transmitted to the system through a wireless interface.

15. The system of claim 1, wherein the respective logic and digital signal processing configuration information are each embodied as a plurality of discrete information data packets.

16. The system of claim 1, wherein the respective logic and digital signal processing configuration information are each embodied as a stream of information data bits.

17. The system of claim 1, wherein the configurable logic computational unit is further configured to generate a request for another logic configuration information to reconfigure the first plurality of computational elements to perform another logic function.

18. The system of claim 17, wherein the configurable logic computational unit is further configured to determine a system configuration capacity prior to utilizing the other logic configuration information to reconfigure for the other logic function.

19. The system of claim 1, wherein the digital signal processing computational unit is further configured to determine a system configuration capacity prior to utilizing the second digital signal processing configuration information to configure for the second digital signal processing function.

20. The system of claim 1, wherein the second plurality of heterogeneous computational elements of the digital signal processing computational unit includes a multiplier computational element and an adder computational element.

21. The system of claim 1, wherein the first plurality of computational elements is different than the second plurality of heterogeneous computational elements.

22. The system of claim 1, wherein the respective configuration information is each received by the system before being stored in the memory.

23. The system of claim 1, wherein the received respective configuration information is each encrypted.

24. The system of claim 1, wherein the received respective configuration information were each transmitted to the system in response to a request sent by the system.

37. The system of claim 1, wherein at least the first and second logic configuration information are stored at different times;

and

wherein at least the first and second digital signal processing configuration information are stored at different times.

38. The system of claim 1, wherein at least the first and second logic configuration information are stored at same time;

and

wherein at least the first and second digital signal processing configuration information are stored at the same time.

39. The system of claim 1, wherein the configurable logic computational unit operates at the bit level;

and

wherein the configurable digital signal processing computational unit operates at the word level or the bit level.

25. A system for adaptive configuration, the system comprising:

a memory;

a configurable logic computational unit including a first plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components and a configurable logic interconnection network for forming a first configurable architecture, the configurable logic interconnection network configurably coupling the first plurality of computational elements together, the configurable logic interconnection network adapted to configure the first plurality of computational elements for performing a first logic function in response to first logic configuration information stored by the memory, the configurable logic interconnection network further adapted to reconfigure the first plurality of computational elements for performing a second logic function in response to second logic configuration information stored by the memory; and

a configurable digital signal processing computational unit including a second plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous and a digital signal processing interconnection network for forming a second configurable architecture, the digital signal processing interconnection network configurably coupling the second plurality of computational elements, the second plurality of computational elements including a multiplier computational element and an adder computational element, the digital signal processing interconnection network adapted to configure the second plurality of computational elements for performing a first digital signal processing function in response to first digital signal processing configuration information stored by the memory, the digital signal processing interconnection network further adapted to configure the second plurality of computational elements for performing a second digital signal processing function in response to second digital signal processing configuration information stored by the memory.

26. The system of claim 25, wherein the first plurality of computational elements of the configurable logic computational unit may include an adder, a register, or a function generator having data inputs and a control input to select a specific function.

27. The system of claim 25, wherein the digital signal processing interconnection network includes multiplexers configurably coupled to the multiplier and adder computational elements, the multiplexers configurably routing data between the multiplier and adder computational elements.

28. The system of claim 25, wherein the digital signal processing interconnection network provides another configuration information to configure the digital signal processing computational unit to perform another function.

29. The system of claim 28, wherein the other function is one of fixed point arithmetic functions, floating point arithmetic functions, filter functions, and transformation functions.

30. The system of claim 25, wherein the heterogeneous computational elements of the configurable digital signal processing computational unit each perform a function from the group of subtraction, accumulation, summation and dynamic shift.

31. The system of claim 25, wherein the first plurality of computational elements is different than the second plurality of heterogeneous computational elements.

40. The system of claim 25, wherein at least the first and second logic configuration information are stored at different times;

and

wherein at least the first and second digital signal processing configuration information are stored at different times.

41. The system of claim 25, wherein at least the first and second logic configuration information are stored at same time;

and

wherein at least the first and second digital signal processing configuration information are stored at the same time.

42. The system of claim 25, wherein the configurable logic computational unit operates at the bit level;

and

wherein the configurable digital signal processing computational unit operates at the word level or the bit level.

32. A system for adaptive configuration, the system comprising:

a memory;

a first configurable computational unit having a first configurable architecture including a first plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components and a configurable logic interconnection network configurably coupling the first plurality of computational elements, the configurable logic interconnection network adapted to configure the first plurality of computational elements for performing a first logic function in response to first logic configuration information stored by the memory, the configurable logic interconnection network further adapted to configure the first plurality of computational elements for performing a second logic function in response to second logic configuration information stored by the memory; and

a second configurable computational unit having a second configurable architecture including a second plurality of computational elements and a digital signal processing interconnection network configurably coupling the second plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous, the second plurality of elements including a first type of computational element and a second type of computational element, the digital signal processing interconnection network adapted to configure the second plurality of computational elements for performing a first digital signal processing function in response to first digital signal processing configuration information stored by the memory by bypassing the first type of computational element, the digital signal processing interconnection network further adapted to configure the second plurality of computational elements for performing a second digital signal processing function in response to second digital signal processing configuration information stored by the memory by connecting the first and second types of computational elements.

33. The system of claim 32, wherein the computational elements of the first configurable computational unit are each one of a group of an adder, a register, or a function generator having data inputs and a control input to select a specific function.

34. The system of claim 32, wherein the digital signal processing interconnection network includes multiplexers configurably coupled to the two types of computational elements, the multiplexers configurably routing data between the two types of computational elements.

35. The system of claim 32, wherein the heterogeneous computational elements of the second configurable computational unit each perform a function from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

36. The system of claim 32, wherein the first plurality of computational elements is different than the second plurality of heterogeneous computational elements.

43. The system of claim 32, wherein at least the first and second logic configuration information are stored at different times;

and

wherein at least the first and second digital signal processing configuration information are stored at different times.

44. The system of claim 32, wherein at least the first and second logic configuration information are stored at same time;

and

wherein at least the first and second digital signal processing configuration information are stored at the same time.

45. The system of claim 32, wherein the first configurable computational unit operates at the bit level;

and

wherein the second configurable computational unit operates at the word level or the bit level.