Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
First Claim
1. A system for adaptive configuration, the system comprising:
- a memory;
a configurable logic computational unit having a first configurable architecture including a first plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components and a configurable logic interconnection network configurably coupling the first plurality of computational elements, the configurable logic interconnection network adapted to configure the first plurality of computational elements for performing a first logic function in response to first logic configuration information stored by the memory, the configurable logic interconnection network further adapted to reconfigure the first plurality of computational elements for performing a second logic function in response to second logic configuration information stored by the memory; and
a configurable digital signal processing computational unit having a second configurable architecture including a second plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous and a digital signal processing interconnection network configurably coupling the second plurality of computational elements together, the digital signal processing interconnection network adapted to configure the second plurality of computational elements for performing a first digital signal processing function in response to first digital signal processing configuration information stored by the memory, the digital signal processing interconnection network further adapted to configure the second plurality of computational elements for performing a second digital signal processing function in response to second digital signal processing configuration information stored by the memory.
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Accused Products
Abstract
The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.
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Citations
45 Claims
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1. A system for adaptive configuration, the system comprising:
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a memory; a configurable logic computational unit having a first configurable architecture including a first plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components and a configurable logic interconnection network configurably coupling the first plurality of computational elements, the configurable logic interconnection network adapted to configure the first plurality of computational elements for performing a first logic function in response to first logic configuration information stored by the memory, the configurable logic interconnection network further adapted to reconfigure the first plurality of computational elements for performing a second logic function in response to second logic configuration information stored by the memory; and a configurable digital signal processing computational unit having a second configurable architecture including a second plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous and a digital signal processing interconnection network configurably coupling the second plurality of computational elements together, the digital signal processing interconnection network adapted to configure the second plurality of computational elements for performing a first digital signal processing function in response to first digital signal processing configuration information stored by the memory, the digital signal processing interconnection network further adapted to configure the second plurality of computational elements for performing a second digital signal processing function in response to second digital signal processing configuration information stored by the memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 37, 38, 39)
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25. A system for adaptive configuration, the system comprising:
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a memory; a configurable logic computational unit including a first plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components and a configurable logic interconnection network for forming a first configurable architecture, the configurable logic interconnection network configurably coupling the first plurality of computational elements together, the configurable logic interconnection network adapted to configure the first plurality of computational elements for performing a first logic function in response to first logic configuration information stored by the memory, the configurable logic interconnection network further adapted to reconfigure the first plurality of computational elements for performing a second logic function in response to second logic configuration information stored by the memory; and a configurable digital signal processing computational unit including a second plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous and a digital signal processing interconnection network for forming a second configurable architecture, the digital signal processing interconnection network configurably coupling the second plurality of computational elements, the second plurality of computational elements including a multiplier computational element and an adder computational element, the digital signal processing interconnection network adapted to configure the second plurality of computational elements for performing a first digital signal processing function in response to first digital signal processing configuration information stored by the memory, the digital signal processing interconnection network further adapted to configure the second plurality of computational elements for performing a second digital signal processing function in response to second digital signal processing configuration information stored by the memory. - View Dependent Claims (26, 27, 28, 29, 30, 31, 40, 41, 42)
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32. A system for adaptive configuration, the system comprising:
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a memory; a first configurable computational unit having a first configurable architecture including a first plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components and a configurable logic interconnection network configurably coupling the first plurality of computational elements, the configurable logic interconnection network adapted to configure the first plurality of computational elements for performing a first logic function in response to first logic configuration information stored by the memory, the configurable logic interconnection network further adapted to configure the first plurality of computational elements for performing a second logic function in response to second logic configuration information stored by the memory; and a second configurable computational unit having a second configurable architecture including a second plurality of computational elements and a digital signal processing interconnection network configurably coupling the second plurality of computational elements at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous, the second plurality of elements including a first type of computational element and a second type of computational element, the digital signal processing interconnection network adapted to configure the second plurality of computational elements for performing a first digital signal processing function in response to first digital signal processing configuration information stored by the memory by bypassing the first type of computational element, the digital signal processing interconnection network further adapted to configure the second plurality of computational elements for performing a second digital signal processing function in response to second digital signal processing configuration information stored by the memory by connecting the first and second types of computational elements. - View Dependent Claims (33, 34, 35, 36, 43, 44, 45)
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Specification