Wake-and-go mechanism with data exclusivity

• US 8,225,120 B2
• Filed: 02/01/2008
• Issued: 07/17/2012
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Brown, Michael J
• Application Number:
  US12/024,479
• Publication Number:
  US 20090199028A1
• Time in Patent Office: 1,628 Days
• Field of Search: 713/300, 713/320, 713/323, 718/104
• US Class Current: 713/323
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

Snoop response logic on a system bus is configured to detect on the system bus requests to access data at a target address with data exclusivity from at least one of a plurality of wake-and-go engines. The snoop response logic is further configured to determine a winning wake-and-go engine from the at least one wake-and-go engine that obtains a lock on the target address and generate a combined snoop response. The combined snoop response identifies the winning wake-and-go engine. The snoop response logic sends the combined snoop response to the at least one wake-and-go engine on the system bus. Each remaining wake-and-go engine within the at least one wake-and-go engine places an entry in its respective wake-and-go storage array to spin on a lock for the target address.

Claims

1. A method, in a data processing system, for determining data exclusivity for wake-and-go engines, the method comprising:

detecting, by a first wake-and-go engine within a plurality of wake-and-go engines connected to a system bus in a multiple processor system, a thread that is waiting for an event associated with a target address, wherein the thread executes on a first processor in the multiple processor system;

performing, by the first wake-and-go engine, a look-ahead load operation without reservation at the target address on behalf of the thread;

receiving, by the first wake-and-go engine, a system bus response from at least one other wake-and-go engine within the plurality of wake-and-go engines;

determining, by the first wake-and-go engine, whether a second wake-and-go engine within the plurality of wake-and-go engines has exclusivity with respect to the target address based on the system bus response; and

responsive to the first wake-and-go engine determining the second wake-and-go engine has exclusivity with respect to the target address, placing, by the first wake-and-go engine, an entry storing the target address in its respective wake-and-go storage array to spin on a lock for the target address on behalf of the thread by snooping the system bus for the target address without exclusivity.

2. The method of claim 1, further comprising:

responsive to the first wake-and-go engine determining no other wake-and-go engine has exclusivity with respect to the target address, performing, by the first wake-and-go engine, a comparison of a data value read in the look-ahead load operation with an expected value;

determining, by the first wake-and-go engine, whether the event associated with the target address has occurred based on the comparison; and

responsive to the first wake-and-go engine determining the event associated with the target address has occurred, performing, by the first wake-and-go engine, a load with reservation operation to request exclusivity with respect to the target address on behalf of the thread.

3. The method of claim 2, further comprising:

responsive to the first wake-and-go engine determining the event associated with the target address has not occurred, placing, by the first wake-and-go engine, an entry storing the target address in its respective wake-and-go storage array to spin on a lock for the target address on behalf of the thread by snooping the system bus for the target address without exclusivity.

4. The method of claim 2, further comprising:

responsive to the load with reservation operation, determining whether the first wake-and-go engine has obtained exclusivity with respect to the target address; and

responsive to the first wake-and go engine not having exclusivity with respect to the target address, placing, by the first wake-and-go engine, an entry storing the target address in its respective wake-and-go storage array to spin on a lock for the target address on behalf of the thread by snooping the system bus for the target address without exclusivity.

5. The method of claim 4, further comprising:

responsive to the first wake-and-go engine having exclusivity with respect to the target address, continuing operation of the thread on the first processor.

6. The method of claim 1, further comprising:

responsive to the first wake-and-go engine detecting the target address on the system bus, performing, by the first wake-and-go engine, a load without reservation operation at the target address on behalf of the thread;

performing, by the first wake-and-go engine, a comparison of a data value read in the load without reservation operation with an expected value; and

determining, by the first wake-and-go engine, whether the event associated with the target address has occurred based on the comparison.

7. The method of claim 6, further comprising:

responsive to the first wake-and-go engine determining the event associated with the target address has occurred, performing, by the first wake-and-go engine, a load with reservation operation to request exclusivity with respect to the target address on behalf of the thread.

8. The method of claim 1, wherein the look-ahead load command is a specialized bus command indicating that the given wake-and-go engine is performing a look-ahead polling operation without caching or data exclusivity.

9. A data processing system, comprising:

a plurality of wake-and-go engines, wherein each of the plurality of wake-and-go engines is associated with a processor and has a respective wake-and-go storage array; and

a system bus,

wherein a first wake-and-go engine within the plurality of wake-and-go engines is configured to;

detect a thread that is waiting for an event associated with a target address, wherein the thread executes on a first processor;

perform a look-ahead load operation without reservation at the target address on behalf of the thread;

receive a system bus response from at least one other wake-and-go engine within the plurality of wake-and-go engines;

determine whether a second wake-and-go engine within the plurality of wake-and-go engines has exclusivity with respect to the target address based on the system bus response; and

responsive to the first wake-and-go engine determining the second wake-and-go engine has exclusivity with respect to the target address, place an entry storing the target address in its respective wake-and-go storage array to spin on a lock for the target address on behalf of the thread by snooping the system bus for the target address without exclusivity.

10. The data processing system of claim 9, wherein the first wake-and-go engine is further configured to:

responsive to the first wake-and-go engine determining no other wake-and-go engine has exclusivity with respect to the target address, perform a comparison of a data value read in the look-ahead load operation with an expected value;

determine whether the event associated with the target address has occurred based on the comparison; and

responsive to the first wake-and-go engine determining the event associated with the target address has occurred, perform a load with reservation operation to request exclusivity with respect to the target address on behalf of the thread.

11. The data processing system of claim 10, wherein the first wake-and-go engine is further configured to:

responsive to the first wake-and-go engine determining the event associated with the target address has not occurred, place an entry storing the target address in its respective wake-and-go storage array to spin on a lock for the target address on behalf of the thread by snooping the system bus for the target address without exclusivity.

12. The data processing system of claim 10, wherein the first wake-and-go engine is further configured to:

responsive to the load with reservation operation, determine whether the first wake-and-go engine has obtained exclusivity with respect to the target address; and

responsive to the first wake-and-go engine not having exclusivity with respect to the target address, placing, by the first wake-and-go engine, an entry storing the target address in its respective wake-and-go storage array to spin on a lock for the target address on behalf of the thread by snooping the system bus for the target address without exclusivity.

13. The data processing system of claim 12, wherein the first wake-and-go engine is further configured to:

responsive to the first wake-and-go engine having exclusivity with respect to the target address, continuing operation of the thread on the first processor.

14. The data processing system of claim 9, wherein the each respective wake-and-go storage array comprises a content addressable memory.

15. The data processing system of claim 9, wherein the first wake-and-go engine is further configured to:

responsive to the first wake-and-go engine detecting the target address on the system bus, perform a load without reservation operation at the target address on behalf of the thread;

perform a comparison of a data value read in the load without reservation operation with an expected value; and

determine whether the event associated with the target address has occurred based on the comparison.

16. The data processing system of claim 15, wherein the first wake-and-go engine is further configured to:

responsive to the first wake-and-go engine determining the event associated with the target address has occurred. performing, by the first wake-and-go engine, a load with reservation operation to request exclusivity with respect to the target address on behalf of the thread.

17. The data processing system of claim 9, wherein the look-ahead load command is a specialized bus command indicating that the given wake-and-go engine is performing a look-ahead polling operation without caching or data exclusivity.

18. A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a first wake-and-go engine within a plurality of wake-and-go engines connected to a system bus in a multiple processor system, causes the first wake-and-go engine to:

detect a thread that is waiting for an event associated with a target address, wherein the thread executes on a first processor;

perform a look-ahead load operation without reservation at the target address on behalf of the thread;

receive a system bus response from at least one other wake-and-go engine within the plurality of wake-and-go engines;

determine whether a second wake-and-go engine within the plurality of wake-and-go engines has exclusivity with respect to the target address based on the system bus response; and

responsive to the first wake-and-go engine determining the second wake-and-go engine has exclusivity with respect to the target address, place an entry storing the target address in its respective wake-and-go storage array to spin on a lock for the target address on behalf of the thread by snooping the system bus for the target address without exclusivity.

19. The computer program product of claim 18, wherein the computer readable program further causes the first wake-and-go engine to:

responsive to the first wake-and-go engine determining no other wake-and-go engine has exclusivity with respect to the target address, perform a comparison of a data value read in the look-ahead load operation with an expected value;

determine whether the event associated with the target address has occurred based on the comparison; and

responsive to the first wake-and-go engine determining the event associated with the target address has occurred, perform a load with reservation operation to request exclusivity with respect to the target address on behalf of the thread.

20. The computer program product of claim 18, wherein the computer readable program further causes the first wake-and-go engine to:

responsive to the first wake-and-go engine detecting the target address on the system bus, perform a load without reservation operation at the target address on behalf of the thread;

perform a comparison of a data value read in the look-ahead load operation with an expected value; and

determine whether the event associated with the target address has occurred based on the comparison.