Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device

• US 8,225,243 B2
• Filed: 11/17/2009
• Issued: 07/17/2012
• Est. Priority Date: 04/17/2002
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Koga, Chiaki, Tsuda, Masayuki, Nakayama, Akitsugu
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US12/591,356
• Publication Number:
  US 20100070943A1
• Time in Patent Office: 973 Days
• Field of Search: 716100-104, 716116-117, 716/121, 716/128
• US Class Current: 716/101
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Claims

1. A concurrent development system for concurrent development of an ASIC and a programmable logic device used by a user from a computer connected to a network, comprising:

an ASIC logic synthesis unit that executes logic synthesis of the ASIC in response to a request from the user, to obtain a first logic synthesis result;

an ASIC logic synthesis result determining unit that determines whether the first logic synthesis result satisfies a speed performance required by the user, to obtain a determination result;

a programmable logic device logic synthesis unit that executes logic synthesis of the programmable logic device, based on the determination result to obtain a second logic synthesis result;

a logic synthesis result displaying unit that displays the first logic synthesis result and the second logic synthesis result on the computer; and

a logic synthesis informing unit that informs the user by an e-mail, of start of the logic synthesis of the ASIC and the first logic synthesis result, and of start of the logic synthesis of the programmable logic device and the second logic synthesis result.

2. The concurrent development system for concurrent development of an ASIC and a programmable logic device according to claim 1, further comprising:

a netlist creating unit that creates a netlist including port connection information of a plurality of functional blocks specified by the user, from functional blocks constituting the ASIC, in response to a request of the user;

a ROM data creating unit that creates ROM data, in which a circuit of the programmable logic device is recorded, by inserting logic synthesized data of the plurality of functional blocks into the netlist created by the netlist creating unit;

a ROM data creation result display unit that displays a result of the creation of the ROM data, on the computer; and

a ROM data creation result informing unit that informs the user by an e-mail, of the result of creation of the ROM data.

3. The concurrent development system for concurrent development of an ASIC and a programmable logic device according to claim 2, further comprising:

a temporary netlist creating unit that creates a netlist in which a dummy circuit is inserted in an input terminal and an output terminal of the functional block constituting the ASIC specified by the user, when designing of the functional block has not been completed, and when there is no circuit data.

4. The concurrent development system for concurrent development of an ASIC and a programmable logic device according to claim 1, further comprising:

a monitoring unit that monitors the latest circuit data the user has and the scale of change in the circuit data incorporated in an implementation design by an implementation designer, to thereby obtain a monitoring result;

a change timing informing unit that informs the user and the implementation designer of the ASIC by an e-mail that it is time to reflect the change monitored, based on the monitoring result and the time required for the layout designing, at a scheduled date and time; and

a reflection suspension requesting unit using which the user requests suspension of reflecting the change monitored, by altering the date for reflecting the change monitored, in response to the e-mail.

5. A concurrent development method for concurrent development of an ASIC and a programmable logic device used by a user from a computer connected to a network, comprising:

a first executing including executing, by using a computer, logic synthesis of the ASIC in response to a request from the user, to obtain a first logic synthesis result;

determining whether the first logic synthesis result satisfies a speed performance required by the user, to obtain a determination result;

a second executing including executing logic synthesis of the programmable logic device, based on the determination result to obtain a second logic synthesis result;

displaying the first logic synthesis result and the second logic synthesis result on the computer; and

informing the user by an e-mail, of start of the first executing and the first logic synthesis result, and of start of the second executing and the second logic synthesis result.